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439d6e3c64
This is part of https://bugs.llvm.org/show_bug.cgi?id=40442. Vector legalization is implemented for the add/sub overflow opcodes. UMULO/SMULO are also handled as far as legalization is concerned, but they don't support vector expansion yet (so no tests for them). The vector result widening implementation is suboptimal, because it could result in a legalization loop. Differential Revision: https://reviews.llvm.org/D57639 llvm-svn: 353464
320 lines
12 KiB
LLVM
320 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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declare {<1 x i32>, <1 x i1>} @llvm.uadd.with.overflow.v1i32(<1 x i32>, <1 x i32>)
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declare {<2 x i32>, <2 x i1>} @llvm.uadd.with.overflow.v2i32(<2 x i32>, <2 x i32>)
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declare {<3 x i32>, <3 x i1>} @llvm.uadd.with.overflow.v3i32(<3 x i32>, <3 x i32>)
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declare {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32>, <4 x i32>)
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declare {<6 x i32>, <6 x i1>} @llvm.uadd.with.overflow.v6i32(<6 x i32>, <6 x i32>)
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declare {<8 x i32>, <8 x i1>} @llvm.uadd.with.overflow.v8i32(<8 x i32>, <8 x i32>)
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declare {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8>, <16 x i8>)
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declare {<8 x i16>, <8 x i1>} @llvm.uadd.with.overflow.v8i16(<8 x i16>, <8 x i16>)
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declare {<2 x i64>, <2 x i1>} @llvm.uadd.with.overflow.v2i64(<2 x i64>, <2 x i64>)
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declare {<4 x i24>, <4 x i1>} @llvm.uadd.with.overflow.v4i24(<4 x i24>, <4 x i24>)
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declare {<4 x i1>, <4 x i1>} @llvm.uadd.with.overflow.v4i1(<4 x i1>, <4 x i1>)
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declare {<2 x i128>, <2 x i1>} @llvm.uadd.with.overflow.v2i128(<2 x i128>, <2 x i128>)
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define <1 x i32> @uaddo_v1i32(<1 x i32> %a0, <1 x i32> %a1, <1 x i32>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v1i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.2s, v0.2s, v1.2s
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; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: str s1, [x0]
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; CHECK-NEXT: ret
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%t = call {<1 x i32>, <1 x i1>} @llvm.uadd.with.overflow.v1i32(<1 x i32> %a0, <1 x i32> %a1)
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%val = extractvalue {<1 x i32>, <1 x i1>} %t, 0
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%obit = extractvalue {<1 x i32>, <1 x i1>} %t, 1
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%res = sext <1 x i1> %obit to <1 x i32>
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store <1 x i32> %val, <1 x i32>* %p2
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ret <1 x i32> %res
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}
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define <2 x i32> @uaddo_v2i32(<2 x i32> %a0, <2 x i32> %a1, <2 x i32>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.2s, v0.2s, v1.2s
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; CHECK-NEXT: cmhi v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: str d1, [x0]
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; CHECK-NEXT: ret
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%t = call {<2 x i32>, <2 x i1>} @llvm.uadd.with.overflow.v2i32(<2 x i32> %a0, <2 x i32> %a1)
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%val = extractvalue {<2 x i32>, <2 x i1>} %t, 0
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%obit = extractvalue {<2 x i32>, <2 x i1>} %t, 1
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%res = sext <2 x i1> %obit to <2 x i32>
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store <2 x i32> %val, <2 x i32>* %p2
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ret <2 x i32> %res
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}
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define <3 x i32> @uaddo_v3i32(<3 x i32> %a0, <3 x i32> %a1, <3 x i32>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v3i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: add x8, x0, #8 // =8
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: st1 { v1.s }[2], [x8]
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; CHECK-NEXT: str d1, [x0]
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; CHECK-NEXT: ret
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%t = call {<3 x i32>, <3 x i1>} @llvm.uadd.with.overflow.v3i32(<3 x i32> %a0, <3 x i32> %a1)
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%val = extractvalue {<3 x i32>, <3 x i1>} %t, 0
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%obit = extractvalue {<3 x i32>, <3 x i1>} %t, 1
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%res = sext <3 x i1> %obit to <3 x i32>
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store <3 x i32> %val, <3 x i32>* %p2
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ret <3 x i32> %res
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}
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define <4 x i32> @uaddo_v4i32(<4 x i32> %a0, <4 x i32> %a1, <4 x i32>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.4s, v0.4s, v1.4s
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; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: str q1, [x0]
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; CHECK-NEXT: ret
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%t = call {<4 x i32>, <4 x i1>} @llvm.uadd.with.overflow.v4i32(<4 x i32> %a0, <4 x i32> %a1)
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%val = extractvalue {<4 x i32>, <4 x i1>} %t, 0
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%obit = extractvalue {<4 x i32>, <4 x i1>} %t, 1
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%res = sext <4 x i1> %obit to <4 x i32>
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store <4 x i32> %val, <4 x i32>* %p2
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ret <4 x i32> %res
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}
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define <6 x i32> @uaddo_v6i32(<6 x i32> %a0, <6 x i32> %a1, <6 x i32>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v6i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fmov s0, w6
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; CHECK-NEXT: mov x8, sp
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; CHECK-NEXT: mov v0.s[1], w7
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; CHECK-NEXT: ldr s2, [sp, #16]
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; CHECK-NEXT: ld1 { v0.s }[2], [x8]
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; CHECK-NEXT: add x9, sp, #8 // =8
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; CHECK-NEXT: add x10, sp, #24 // =24
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; CHECK-NEXT: fmov s1, w0
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; CHECK-NEXT: ld1 { v2.s }[1], [x10]
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; CHECK-NEXT: ld1 { v0.s }[3], [x9]
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; CHECK-NEXT: mov v1.s[1], w1
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; CHECK-NEXT: fmov s3, w4
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; CHECK-NEXT: ldr x11, [sp, #32]
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; CHECK-NEXT: mov v1.s[2], w2
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; CHECK-NEXT: mov v3.s[1], w5
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; CHECK-NEXT: mov v1.s[3], w3
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; CHECK-NEXT: add v2.4s, v3.4s, v2.4s
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; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: cmhi v3.4s, v3.4s, v2.4s
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; CHECK-NEXT: cmhi v1.4s, v1.4s, v0.4s
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; CHECK-NEXT: str d2, [x11, #16]
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; CHECK-NEXT: xtn v2.4h, v3.4s
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; CHECK-NEXT: xtn v1.4h, v1.4s
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; CHECK-NEXT: sshll v2.4s, v2.4h, #0
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; CHECK-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-NEXT: mov w5, v2.s[1]
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; CHECK-NEXT: mov w1, v1.s[1]
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; CHECK-NEXT: mov w2, v1.s[2]
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; CHECK-NEXT: mov w3, v1.s[3]
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; CHECK-NEXT: fmov w4, s2
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; CHECK-NEXT: fmov w0, s1
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; CHECK-NEXT: str q0, [x11]
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; CHECK-NEXT: ret
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%t = call {<6 x i32>, <6 x i1>} @llvm.uadd.with.overflow.v6i32(<6 x i32> %a0, <6 x i32> %a1)
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%val = extractvalue {<6 x i32>, <6 x i1>} %t, 0
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%obit = extractvalue {<6 x i32>, <6 x i1>} %t, 1
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%res = sext <6 x i1> %obit to <6 x i32>
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store <6 x i32> %val, <6 x i32>* %p2
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ret <6 x i32> %res
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}
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define <8 x i32> @uaddo_v8i32(<8 x i32> %a0, <8 x i32> %a1, <8 x i32>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v3.4s, v1.4s, v3.4s
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; CHECK-NEXT: add v2.4s, v0.4s, v2.4s
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; CHECK-NEXT: cmhi v1.4s, v1.4s, v3.4s
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; CHECK-NEXT: cmhi v0.4s, v0.4s, v2.4s
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; CHECK-NEXT: xtn v1.4h, v1.4s
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; CHECK-NEXT: xtn v0.4h, v0.4s
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: sshll v1.4s, v1.4h, #0
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; CHECK-NEXT: stp q2, q3, [x0]
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; CHECK-NEXT: ret
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%t = call {<8 x i32>, <8 x i1>} @llvm.uadd.with.overflow.v8i32(<8 x i32> %a0, <8 x i32> %a1)
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%val = extractvalue {<8 x i32>, <8 x i1>} %t, 0
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%obit = extractvalue {<8 x i32>, <8 x i1>} %t, 1
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%res = sext <8 x i1> %obit to <8 x i32>
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store <8 x i32> %val, <8 x i32>* %p2
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ret <8 x i32> %res
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}
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define <16 x i32> @uaddo_v16i8(<16 x i8> %a0, <16 x i8> %a1, <16 x i8>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v4.16b, v0.16b, v1.16b
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; CHECK-NEXT: cmhi v0.16b, v0.16b, v4.16b
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; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b
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; CHECK-NEXT: zip2 v2.8b, v0.8b, v0.8b
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; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: ushll v2.4s, v2.4h, #0
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; CHECK-NEXT: zip1 v3.8b, v0.8b, v0.8b
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; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
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; CHECK-NEXT: shl v1.4s, v1.4s, #31
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; CHECK-NEXT: shl v2.4s, v2.4s, #31
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; CHECK-NEXT: ushll v3.4s, v3.4h, #0
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; CHECK-NEXT: ushll v5.4s, v0.4h, #0
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; CHECK-NEXT: sshr v0.4s, v1.4s, #31
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; CHECK-NEXT: sshr v1.4s, v2.4s, #31
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; CHECK-NEXT: shl v2.4s, v3.4s, #31
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; CHECK-NEXT: shl v3.4s, v5.4s, #31
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; CHECK-NEXT: sshr v2.4s, v2.4s, #31
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; CHECK-NEXT: sshr v3.4s, v3.4s, #31
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; CHECK-NEXT: str q4, [x0]
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; CHECK-NEXT: ret
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%t = call {<16 x i8>, <16 x i1>} @llvm.uadd.with.overflow.v16i8(<16 x i8> %a0, <16 x i8> %a1)
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%val = extractvalue {<16 x i8>, <16 x i1>} %t, 0
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%obit = extractvalue {<16 x i8>, <16 x i1>} %t, 1
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%res = sext <16 x i1> %obit to <16 x i32>
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store <16 x i8> %val, <16 x i8>* %p2
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ret <16 x i32> %res
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}
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define <8 x i32> @uaddo_v8i16(<8 x i16> %a0, <8 x i16> %a1, <8 x i16>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v2.8h, v0.8h, v1.8h
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; CHECK-NEXT: cmhi v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: xtn v0.8b, v0.8h
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; CHECK-NEXT: zip1 v1.8b, v0.8b, v0.8b
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; CHECK-NEXT: zip2 v0.8b, v0.8b, v0.8b
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; CHECK-NEXT: ushll v1.4s, v1.4h, #0
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; CHECK-NEXT: ushll v0.4s, v0.4h, #0
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; CHECK-NEXT: shl v1.4s, v1.4s, #31
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; CHECK-NEXT: shl v3.4s, v0.4s, #31
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; CHECK-NEXT: sshr v0.4s, v1.4s, #31
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; CHECK-NEXT: sshr v1.4s, v3.4s, #31
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; CHECK-NEXT: str q2, [x0]
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; CHECK-NEXT: ret
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%t = call {<8 x i16>, <8 x i1>} @llvm.uadd.with.overflow.v8i16(<8 x i16> %a0, <8 x i16> %a1)
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%val = extractvalue {<8 x i16>, <8 x i1>} %t, 0
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%obit = extractvalue {<8 x i16>, <8 x i1>} %t, 1
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%res = sext <8 x i1> %obit to <8 x i32>
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store <8 x i16> %val, <8 x i16>* %p2
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ret <8 x i32> %res
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}
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define <2 x i32> @uaddo_v2i64(<2 x i64> %a0, <2 x i64> %a1, <2 x i64>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add v1.2d, v0.2d, v1.2d
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; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: str q1, [x0]
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; CHECK-NEXT: ret
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%t = call {<2 x i64>, <2 x i1>} @llvm.uadd.with.overflow.v2i64(<2 x i64> %a0, <2 x i64> %a1)
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%val = extractvalue {<2 x i64>, <2 x i1>} %t, 0
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%obit = extractvalue {<2 x i64>, <2 x i1>} %t, 1
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%res = sext <2 x i1> %obit to <2 x i32>
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store <2 x i64> %val, <2 x i64>* %p2
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ret <2 x i32> %res
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}
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define <4 x i32> @uaddo_v4i24(<4 x i24> %a0, <4 x i24> %a1, <4 x i24>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v4i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: bic v1.4s, #255, lsl #24
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; CHECK-NEXT: bic v0.4s, #255, lsl #24
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; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: mov v1.16b, v0.16b
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; CHECK-NEXT: mov w8, v0.s[3]
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; CHECK-NEXT: bic v1.4s, #255, lsl #24
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; CHECK-NEXT: mov w9, v0.s[2]
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; CHECK-NEXT: mov w10, v0.s[1]
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; CHECK-NEXT: sturh w8, [x0, #9]
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; CHECK-NEXT: lsr w8, w8, #16
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; CHECK-NEXT: cmeq v1.4s, v1.4s, v0.4s
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; CHECK-NEXT: fmov w11, s0
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; CHECK-NEXT: strh w9, [x0, #6]
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; CHECK-NEXT: sturh w10, [x0, #3]
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; CHECK-NEXT: lsr w9, w9, #16
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; CHECK-NEXT: lsr w10, w10, #16
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; CHECK-NEXT: strb w8, [x0, #11]
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; CHECK-NEXT: mvn v0.16b, v1.16b
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; CHECK-NEXT: lsr w8, w11, #16
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; CHECK-NEXT: strh w11, [x0]
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; CHECK-NEXT: strb w9, [x0, #8]
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; CHECK-NEXT: strb w10, [x0, #5]
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; CHECK-NEXT: strb w8, [x0, #2]
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; CHECK-NEXT: ret
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%t = call {<4 x i24>, <4 x i1>} @llvm.uadd.with.overflow.v4i24(<4 x i24> %a0, <4 x i24> %a1)
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%val = extractvalue {<4 x i24>, <4 x i1>} %t, 0
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%obit = extractvalue {<4 x i24>, <4 x i1>} %t, 1
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%res = sext <4 x i1> %obit to <4 x i32>
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store <4 x i24> %val, <4 x i24>* %p2
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ret <4 x i32> %res
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}
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define <4 x i32> @uaddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, <4 x i1>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v4i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v2.4h, #1
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; CHECK-NEXT: and v1.8b, v1.8b, v2.8b
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; CHECK-NEXT: and v0.8b, v0.8b, v2.8b
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; CHECK-NEXT: add v1.4h, v0.4h, v1.4h
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; CHECK-NEXT: umov w9, v1.h[1]
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; CHECK-NEXT: umov w8, v1.h[0]
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; CHECK-NEXT: and w9, w9, #0x1
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; CHECK-NEXT: bfi w8, w9, #1, #1
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; CHECK-NEXT: umov w9, v1.h[2]
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; CHECK-NEXT: and v0.8b, v1.8b, v2.8b
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; CHECK-NEXT: and w9, w9, #0x1
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; CHECK-NEXT: cmeq v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: bfi w8, w9, #2, #1
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; CHECK-NEXT: umov w9, v1.h[3]
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; CHECK-NEXT: mvn v0.8b, v0.8b
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; CHECK-NEXT: bfi w8, w9, #3, #29
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; CHECK-NEXT: sshll v0.4s, v0.4h, #0
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; CHECK-NEXT: and w8, w8, #0xf
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; CHECK-NEXT: strb w8, [x0]
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; CHECK-NEXT: ret
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%t = call {<4 x i1>, <4 x i1>} @llvm.uadd.with.overflow.v4i1(<4 x i1> %a0, <4 x i1> %a1)
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%val = extractvalue {<4 x i1>, <4 x i1>} %t, 0
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%obit = extractvalue {<4 x i1>, <4 x i1>} %t, 1
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%res = sext <4 x i1> %obit to <4 x i32>
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store <4 x i1> %val, <4 x i1>* %p2
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ret <4 x i32> %res
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}
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define <2 x i32> @uaddo_v2i128(<2 x i128> %a0, <2 x i128> %a1, <2 x i128>* %p2) nounwind {
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; CHECK-LABEL: uaddo_v2i128:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adds x9, x2, x6
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; CHECK-NEXT: adcs x10, x3, x7
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; CHECK-NEXT: cmp x9, x2
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; CHECK-NEXT: cset w11, lo
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; CHECK-NEXT: cmp x10, x3
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; CHECK-NEXT: cset w12, lo
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; CHECK-NEXT: csel w11, w11, w12, eq
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; CHECK-NEXT: adds x12, x0, x4
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; CHECK-NEXT: adcs x13, x1, x5
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; CHECK-NEXT: cmp x12, x0
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; CHECK-NEXT: cset w14, lo
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; CHECK-NEXT: cmp x13, x1
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; CHECK-NEXT: cset w15, lo
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; CHECK-NEXT: csel w14, w14, w15, eq
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; CHECK-NEXT: ldr x8, [sp]
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; CHECK-NEXT: fmov s0, w14
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; CHECK-NEXT: mov v0.s[1], w11
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; CHECK-NEXT: shl v0.2s, v0.2s, #31
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; CHECK-NEXT: sshr v0.2s, v0.2s, #31
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; CHECK-NEXT: stp x9, x10, [x8, #16]
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; CHECK-NEXT: stp x12, x13, [x8]
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; CHECK-NEXT: ret
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%t = call {<2 x i128>, <2 x i1>} @llvm.uadd.with.overflow.v2i128(<2 x i128> %a0, <2 x i128> %a1)
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%val = extractvalue {<2 x i128>, <2 x i1>} %t, 0
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%obit = extractvalue {<2 x i128>, <2 x i1>} %t, 1
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%res = sext <2 x i1> %obit to <2 x i32>
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store <2 x i128> %val, <2 x i128>* %p2
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ret <2 x i32> %res
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}
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