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f60a29f8fa
We fail to canonicalize IR this way (prefer 'not' ops to arbitrary 'xor'), but that would not matter without this patch because DAGCombiner was reversing that transform. I think we need this transform in the backend regardless of what happens in IR to catch cases where the shift-xor is formed late from GEP or other ops. https://rise4fun.com/Alive/NC1 Name: shl Pre: (-1 << C2) == C1 %shl = shl i8 %x, C2 %r = xor i8 %shl, C1 => %not = xor i8 %x, -1 %r = shl i8 %not, C2 Name: shr Pre: (-1 u>> C2) == C1 %sh = lshr i8 %x, C2 %r = xor i8 %sh, C1 => %not = xor i8 %x, -1 %r = lshr i8 %not, C2 https://bugs.llvm.org/show_bug.cgi?id=39657 llvm-svn: 347478
18 lines
505 B
LLVM
18 lines
505 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
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define i32 @PR39657(i8* %p, i64 %x) {
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; CHECK-LABEL: PR39657:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mvn x8, x1
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; CHECK-NEXT: ldr w0, [x0, x8, lsl #2]
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; CHECK-NEXT: ret
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%sh = shl i64 %x, 2
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%mul = xor i64 %sh, -4
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%add.ptr = getelementptr inbounds i8, i8* %p, i64 %mul
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%bc = bitcast i8* %add.ptr to i32*
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%load = load i32, i32* %bc, align 4
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ret i32 %load
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}
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