llvm-mirror/test/CodeGen/AArch64/zext-logic-shift-load.ll
Guozhi Wei fb70343484 [DAGCombiner] Fold (zext (and/or/xor (shl/shr (load x), cst), cst))
In our real world application, we found the following optimization is missed in DAGCombiner

(zext (and/or/xor (shl/shr (load x), cst), cst)) -> (and/or/xor (shl/shr (zextload x), (zext cst)), (zext cst))

If the user of original zext is an add, it may enable further lea optimization on x86.

This patch add a new function CombineZExtLogicopShiftLoad to do this optimization.

Differential Revision: https://reviews.llvm.org/D44402

llvm-svn: 329516
2018-04-07 23:36:10 +00:00

15 lines
257 B
LLVM

; RUN: llc -mtriple=aarch64-linux-gnu < %s -o - | FileCheck %s
define i32 @test1(i8* %p) {
; CHECK: ldrb
; CHECK-NEXT: ubfx
; CHECK-NEXT: ret
%1 = load i8, i8* %p
%2 = lshr i8 %1, 1
%3 = and i8 %2, 1
%4 = zext i8 %3 to i32
ret i32 %4
}