mirror of
https://github.com/RPCS3/llvm-mirror.git
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9b9d97f26a
Previously, subtarget features were a bitfield with the underlying type being uint64_t. Since several targets (X86 and ARM, in particular) have hit or were very close to hitting this bound, switching the features to use a bitset. No functional change. The first several times this was committed (e.g. r229831, r233055), it caused several buildbot failures. Apparently the reason for most failures was both clang and gcc's inability to deal with large numbers (> 10K) of bitset constructor calls in tablegen-generated initializers of instruction info tables. This should now be fixed. llvm-svn: 238192
402 lines
14 KiB
C++
402 lines
14 KiB
C++
//===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "llvm/MC/MCDisassembler.h"
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#include "llvm/MC/MCFixedLenDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/TargetRegistry.h"
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using namespace llvm;
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#define DEBUG_TYPE "ppc-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class PPCDisassembler : public MCDisassembler {
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public:
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PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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~PPCDisassembler() override {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &VStream,
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raw_ostream &CStream) const override;
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};
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} // end anonymous namespace
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static MCDisassembler *createPPCDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new PPCDisassembler(STI, Ctx);
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}
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extern "C" void LLVMInitializePowerPCDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(ThePPC32Target,
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createPPCDisassembler);
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TargetRegistry::RegisterMCDisassembler(ThePPC64Target,
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createPPCDisassembler);
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TargetRegistry::RegisterMCDisassembler(ThePPC64LETarget,
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createPPCDisassembler);
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}
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// FIXME: These can be generated by TableGen from the existing register
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// encoding values!
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static const unsigned CRRegs[] = {
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PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
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PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
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};
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static const unsigned CRBITRegs[] = {
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PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
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PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
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PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
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PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
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PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
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PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
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PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
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PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
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};
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static const unsigned FRegs[] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31
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};
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static const unsigned VRegs[] = {
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PPC::V0, PPC::V1, PPC::V2, PPC::V3,
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PPC::V4, PPC::V5, PPC::V6, PPC::V7,
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PPC::V8, PPC::V9, PPC::V10, PPC::V11,
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PPC::V12, PPC::V13, PPC::V14, PPC::V15,
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PPC::V16, PPC::V17, PPC::V18, PPC::V19,
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PPC::V20, PPC::V21, PPC::V22, PPC::V23,
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31
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};
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static const unsigned VSRegs[] = {
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PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3,
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PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7,
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PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11,
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PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
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PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
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PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
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PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
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PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
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PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3,
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PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7,
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PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11,
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PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
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PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
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PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
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PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
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PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
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};
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static const unsigned VSFRegs[] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31,
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PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
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PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
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PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
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PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
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PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
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PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
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PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
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PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
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};
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static const unsigned VSSRegs[] = {
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PPC::F0, PPC::F1, PPC::F2, PPC::F3,
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PPC::F4, PPC::F5, PPC::F6, PPC::F7,
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PPC::F8, PPC::F9, PPC::F10, PPC::F11,
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PPC::F12, PPC::F13, PPC::F14, PPC::F15,
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PPC::F16, PPC::F17, PPC::F18, PPC::F19,
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PPC::F20, PPC::F21, PPC::F22, PPC::F23,
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PPC::F24, PPC::F25, PPC::F26, PPC::F27,
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PPC::F28, PPC::F29, PPC::F30, PPC::F31,
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PPC::VF0, PPC::VF1, PPC::VF2, PPC::VF3,
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PPC::VF4, PPC::VF5, PPC::VF6, PPC::VF7,
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PPC::VF8, PPC::VF9, PPC::VF10, PPC::VF11,
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PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
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PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
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PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
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PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
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PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
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};
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static const unsigned GPRegs[] = {
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PPC::R0, PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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PPC::R8, PPC::R9, PPC::R10, PPC::R11,
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PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31
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};
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static const unsigned GP0Regs[] = {
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PPC::ZERO, PPC::R1, PPC::R2, PPC::R3,
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PPC::R4, PPC::R5, PPC::R6, PPC::R7,
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PPC::R8, PPC::R9, PPC::R10, PPC::R11,
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PPC::R12, PPC::R13, PPC::R14, PPC::R15,
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PPC::R16, PPC::R17, PPC::R18, PPC::R19,
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PPC::R20, PPC::R21, PPC::R22, PPC::R23,
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PPC::R24, PPC::R25, PPC::R26, PPC::R27,
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PPC::R28, PPC::R29, PPC::R30, PPC::R31
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};
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static const unsigned G8Regs[] = {
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PPC::X0, PPC::X1, PPC::X2, PPC::X3,
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PPC::X4, PPC::X5, PPC::X6, PPC::X7,
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PPC::X8, PPC::X9, PPC::X10, PPC::X11,
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PPC::X12, PPC::X13, PPC::X14, PPC::X15,
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PPC::X16, PPC::X17, PPC::X18, PPC::X19,
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PPC::X20, PPC::X21, PPC::X22, PPC::X23,
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PPC::X24, PPC::X25, PPC::X26, PPC::X27,
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PPC::X28, PPC::X29, PPC::X30, PPC::X31
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};
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static const unsigned QFRegs[] = {
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PPC::QF0, PPC::QF1, PPC::QF2, PPC::QF3,
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PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
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PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11,
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PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
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PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
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PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
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PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
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PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
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};
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template <std::size_t N>
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static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
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const unsigned (&Regs)[N]) {
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assert(RegNo < N && "Invalid register number");
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Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRRegs);
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}
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static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRRegs);
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}
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static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, CRBITRegs);
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}
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static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, FRegs);
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}
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static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VRegs);
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}
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static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSRegs);
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}
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static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSFRegs);
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}
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static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, VSSRegs);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, GPRegs);
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}
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static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, GP0Regs);
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}
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static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, G8Regs);
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}
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#define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
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#define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
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static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return decodeRegisterClass(Inst, RegNo, QFRegs);
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}
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#define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
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#define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
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template<unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template<unsigned N>
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static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the memri field (imm, reg), which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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uint64_t Base = Imm >> 16;
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uint64_t Disp = Imm & 0xFFFF;
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assert(Base < 32 && "Invalid base register");
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switch (Inst.getOpcode()) {
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default: break;
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case PPC::LBZU:
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case PPC::LHAU:
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case PPC::LHZU:
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case PPC::LWZU:
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case PPC::LFSU:
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case PPC::LFDU:
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// Add the tied output operand.
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Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
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break;
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case PPC::STBU:
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case PPC::STHU:
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case PPC::STWU:
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case PPC::STFSU:
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case PPC::STFDU:
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Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
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break;
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}
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
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Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// Decode the memrix field (imm, reg), which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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uint64_t Base = Imm >> 14;
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uint64_t Disp = Imm & 0x3FFF;
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assert(Base < 32 && "Invalid base register");
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if (Inst.getOpcode() == PPC::LDU)
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// Add the tied output operand.
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Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
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else if (Inst.getOpcode() == PPC::STDU)
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Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base]));
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Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
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Inst.addOperand(MCOperand::createReg(GP0Regs[Base]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
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int64_t Address, const void *Decoder) {
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// The cr bit encoding is 0x80 >> cr_reg_num.
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unsigned Zeros = countTrailingZeros(Imm);
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assert(Zeros < 8 && "Invalid CR bit value");
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Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
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return MCDisassembler::Success;
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}
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#include "PPCGenDisassemblerTables.inc"
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DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address, raw_ostream &OS,
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raw_ostream &CS) const {
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// Get the four bytes of the instruction.
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Size = 4;
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if (Bytes.size() < 4) {
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Size = 0;
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return MCDisassembler::Fail;
|
|
}
|
|
|
|
// The instruction is big-endian encoded.
|
|
uint32_t Inst =
|
|
(Bytes[0] << 24) | (Bytes[1] << 16) | (Bytes[2] << 8) | (Bytes[3] << 0);
|
|
|
|
if (STI.getFeatureBits()[PPC::FeatureQPX]) {
|
|
DecodeStatus result =
|
|
decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
|
|
if (result != MCDisassembler::Fail)
|
|
return result;
|
|
|
|
MI.clear();
|
|
}
|
|
|
|
return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
|
|
}
|
|
|