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ed09135349
was lowering them to sext / uxt + mul instructions. Unfortunately the optimization passes may hoist the extensions out of the loop and separate them. When that happens, the long multiplication instructions can be broken into several scalar instructions, causing significant performance issue. Note the vmla and vmls intrinsics are not added back. Frontend will codegen them as intrinsics vmull* + add / sub. Also note the isel optimizations for catching mul + sext / zext are not changed either. First part of rdar://8832507, rdar://9203134 llvm-svn: 128502
207 lines
4.2 KiB
LLVM
207 lines
4.2 KiB
LLVM
; RUN: llvm-dis < %s.bc | FileCheck %s
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; vmovls should be auto-upgraded to sext
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; CHECK: vmovls8
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; CHECK-NOT: arm.neon.vmovls.v8i16
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; CHECK: sext <8 x i8>
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; CHECK: vmovls16
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; CHECK-NOT: arm.neon.vmovls.v4i32
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; CHECK: sext <4 x i16>
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; CHECK: vmovls32
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; CHECK-NOT: arm.neon.vmovls.v2i64
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; CHECK: sext <2 x i32>
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; vmovlu should be auto-upgraded to zext
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; CHECK: vmovlu8
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; CHECK-NOT: arm.neon.vmovlu.v8i16
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; CHECK: zext <8 x i8>
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; CHECK: vmovlu16
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; CHECK-NOT: arm.neon.vmovlu.v4i32
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; CHECK: zext <4 x i16>
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; CHECK: vmovlu32
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; CHECK-NOT: arm.neon.vmovlu.v2i64
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; CHECK: zext <2 x i32>
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; vaddl/vaddw should be auto-upgraded to add with sext/zext
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; CHECK: vaddls16
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; CHECK-NOT: arm.neon.vaddls.v4i32
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; CHECK: sext <4 x i16>
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; CHECK-NEXT: sext <4 x i16>
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; CHECK-NEXT: add <4 x i32>
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; CHECK: vaddlu32
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; CHECK-NOT: arm.neon.vaddlu.v2i64
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; CHECK: zext <2 x i32>
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; CHECK-NEXT: zext <2 x i32>
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; CHECK-NEXT: add <2 x i64>
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; CHECK: vaddws8
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; CHECK-NOT: arm.neon.vaddws.v8i16
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; CHECK: sext <8 x i8>
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; CHECK-NEXT: add <8 x i16>
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; CHECK: vaddwu16
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; CHECK-NOT: arm.neon.vaddwu.v4i32
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; CHECK: zext <4 x i16>
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; CHECK-NEXT: add <4 x i32>
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; vsubl/vsubw should be auto-upgraded to subtract with sext/zext
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; CHECK: vsubls16
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; CHECK-NOT: arm.neon.vsubls.v4i32
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; CHECK: sext <4 x i16>
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; CHECK-NEXT: sext <4 x i16>
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; CHECK-NEXT: sub <4 x i32>
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; CHECK: vsublu32
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; CHECK-NOT: arm.neon.vsublu.v2i64
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; CHECK: zext <2 x i32>
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; CHECK-NEXT: zext <2 x i32>
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; CHECK-NEXT: sub <2 x i64>
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; CHECK: vsubws8
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; CHECK-NOT: arm.neon.vsubws.v8i16
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; CHECK: sext <8 x i8>
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; CHECK-NEXT: sub <8 x i16>
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; CHECK: vsubwu16
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; CHECK-NOT: arm.neon.vsubwu.v4i32
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; CHECK: zext <4 x i16>
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; CHECK-NEXT: sub <4 x i32>
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; vmull* intrinsics will remain intrinsics
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; CHECK: vmulls8
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; CHECK: arm.neon.vmulls.v8i16
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; CHECK: vmullu16
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; CHECK: arm.neon.vmullu.v4i32
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; CHECK: vmullp8
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; CHECK: arm.neon.vmullp.v8i16
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; vmlal should be auto-upgraded to multiply/add with sext/zext
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; CHECK: vmlals32
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; CHECK-NOT: arm.neon.vmlals.v2i64
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; CHECK: sext <2 x i32>
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; CHECK-NEXT: sext <2 x i32>
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; CHECK-NEXT: mul <2 x i64>
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; CHECK-NEXT: add <2 x i64>
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; CHECK: vmlalu8
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; CHECK-NOT: arm.neon.vmlalu.v8i16
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; CHECK: zext <8 x i8>
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; CHECK-NEXT: zext <8 x i8>
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; CHECK-NEXT: mul <8 x i16>
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; CHECK-NEXT: add <8 x i16>
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; vmlsl should be auto-upgraded to multiply/sub with sext/zext
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; CHECK: vmlsls16
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; CHECK-NOT: arm.neon.vmlsls.v4i32
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; CHECK: sext <4 x i16>
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; CHECK-NEXT: sext <4 x i16>
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; CHECK-NEXT: mul <4 x i32>
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; CHECK-NEXT: sub <4 x i32>
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; CHECK: vmlslu32
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; CHECK-NOT: arm.neon.vmlslu.v2i64
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; CHECK: zext <2 x i32>
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; CHECK-NEXT: zext <2 x i32>
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; CHECK-NEXT: mul <2 x i64>
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; CHECK-NEXT: sub <2 x i64>
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; vaba should be auto-upgraded to vabd + add
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; CHECK: vabas32
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; CHECK-NOT: arm.neon.vabas.v2i32
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; CHECK: arm.neon.vabds.v2i32
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; CHECK-NEXT: add <2 x i32>
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; CHECK: vabaQu8
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; CHECK-NOT: arm.neon.vabau.v16i8
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; CHECK: arm.neon.vabdu.v16i8
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; CHECK-NEXT: add <16 x i8>
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; vabal should be auto-upgraded to vabd with zext + add
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; CHECK: vabals16
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; CHECK-NOT: arm.neon.vabals.v4i32
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; CHECK: arm.neon.vabds.v4i16
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; CHECK-NEXT: zext <4 x i16>
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; CHECK-NEXT: add <4 x i32>
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; CHECK: vabalu32
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; CHECK-NOT: arm.neon.vabalu.v2i64
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; CHECK: arm.neon.vabdu.v2i32
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; CHECK-NEXT: zext <2 x i32>
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; CHECK-NEXT: add <2 x i64>
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; vabdl should be auto-upgraded to vabd with zext
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; CHECK: vabdls8
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; CHECK-NOT: arm.neon.vabdls.v8i16
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; CHECK: arm.neon.vabds.v8i8
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; CHECK-NEXT: zext <8 x i8>
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; CHECK: vabdlu16
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; CHECK-NOT: arm.neon.vabdlu.v4i32
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; CHECK: arm.neon.vabdu.v4i16
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; CHECK-NEXT: zext <4 x i16>
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; vmovn should be auto-upgraded to trunc
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; CHECK: vmovni16
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; CHECK-NOT: arm.neon.vmovn.v8i8
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; CHECK: trunc <8 x i16>
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; CHECK: vmovni32
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; CHECK-NOT: arm.neon.vmovn.v4i16
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; CHECK: trunc <4 x i32>
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; CHECK: vmovni64
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; CHECK-NOT: arm.neon.vmovn.v2i32
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; CHECK: trunc <2 x i64>
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; vld* and vst* intrinsic calls need an alignment argument (defaulted to 1)
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; CHECK: vld1i8
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; CHECK: i32 1
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; CHECK: vld2Qi16
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; CHECK: i32 1
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; CHECK: vld3i32
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; CHECK: i32 1
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; CHECK: vld4Qf
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; CHECK: i32 1
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; CHECK: vst1i8
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; CHECK: i32 1
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; CHECK: vst2Qi16
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; CHECK: i32 1
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; CHECK: vst3i32
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; CHECK: i32 1
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; CHECK: vst4Qf
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; CHECK: i32 1
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; CHECK: vld2laneQi16
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; CHECK: i32 1
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; CHECK: vld3lanei32
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; CHECK: i32 1
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; CHECK: vld4laneQf
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; CHECK: i32 1
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; CHECK: vst2laneQi16
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; CHECK: i32 1
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; CHECK: vst3lanei32
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; CHECK: i32 1
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; CHECK: vst4laneQf
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; CHECK: i32 1
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