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3d387c31ad
Summary: no-odd-spreg-msa.ll: This test deliberately uses an odd-numbered register in inline assembly and expects the compiler to insert a move to an even-numbered register. inlineasm-operand-code.ll and inlineasm_constraint.ll: Checks for IAS's output will be added once a matcher bug is resolved. This bug causes the canonical output emitted by IAS to be incorrect for uimm16 constants with the MSB set. We will still need the non-IAS checks at this point since these tests primarily test formatting of operands. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D14705 llvm-svn: 254148
164 lines
5.6 KiB
LLVM
164 lines
5.6 KiB
LLVM
; Positive test for inline register constraints
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;
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; RUN: llc -no-integrated-as -march=mipsel < %s | \
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; RUN: FileCheck -check-prefix=ALL -check-prefix=LE32 -check-prefix=GAS %s
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; RUN: llc -no-integrated-as -march=mips < %s | \
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; RUN: FileCheck -check-prefix=ALL -check-prefix=BE32 -check-prefix=GAS %s
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%union.u_tag = type { i64 }
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%struct.anon = type { i32, i32 }
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@uval = common global %union.u_tag zeroinitializer, align 8
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; X with -3
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define i32 @constraint_X() nounwind {
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entry:
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; ALL-LABEL: constraint_X:
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; ALL: #APP
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; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffffffffffffffd
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:X}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; x with -3
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define i32 @constraint_x() nounwind {
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entry:
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; ALL-LABEL: constraint_x:
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; ALL: #APP
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; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, 0xfffd
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:x}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; d with -3
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define i32 @constraint_d() nounwind {
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entry:
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; ALL-LABEL: constraint_d:
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; ALL: #APP
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; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:d}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; m with -3
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define i32 @constraint_m() nounwind {
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entry:
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; ALL-LABEL: constraint_m:
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; ALL: #APP
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; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -4
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:m}", "=r,r,I"(i32 7, i32 -3) ;
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ret i32 0
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}
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; z with -3
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define i32 @constraint_z() nounwind {
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entry:
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; ALL-LABEL: constraint_z:
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; ALL: #APP
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; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, -3
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 -3) ;
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; z with 0
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; ALL: #APP
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; GAS: addiu ${{[0-9]+}}, ${{[0-9]+}}, $0
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; ALL: #NO_APP
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tail call i32 asm sideeffect "addiu $0, $1, ${2:z}", "=r,r,I"(i32 7, i32 0) nounwind
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; z with non-zero and the "r"(register) and "J"(integer zero) constraints
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; ALL: #APP
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; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 7) nounwind
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; z with zero and the "r"(register) and "J"(integer zero) constraints
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; ALL: #APP
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; ALL: mtc0 $0, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "Jr"(i32 0) nounwind
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; z with non-zero and just the "r"(register) constraint
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; ALL: #APP
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; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 7) nounwind
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; z with zero and just the "r"(register) constraint
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; FIXME: Check for $0, instead of other registers.
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; We should be using $0 directly in this case, not real registers.
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; When the materialization of 0 gets fixed, this test will fail.
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; ALL: #APP
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; ALL: mtc0 ${{[1-9][0-9]?}}, ${{[0-9]+}}
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; ALL: #NO_APP
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call void asm sideeffect "mtc0 ${0:z}, $$12", "r"(i32 0) nounwind
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ret i32 0
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}
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; A long long in 32 bit mode (use to assert)
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define i32 @constraint_longlong() nounwind {
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entry:
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; ALL-LABEL: constraint_longlong:
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; ALL: #APP
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; ALL: addiu ${{[0-9]+}}, ${{[0-9]+}}, 3
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; ALL: #NO_APP
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tail call i64 asm sideeffect "addiu $0, $1, $2 \0A\09", "=r,r,X"(i64 1229801703532086340, i64 3) nounwind
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ret i32 0
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}
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; In little endian the source reg will be 4 bytes into the long long
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; In big endian the source reg will also be 4 bytes into the long long
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define i32 @constraint_D() nounwind {
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entry:
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; ALL-LABEL: constraint_D:
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; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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; ALL: #APP
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; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
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; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
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; ALL: #NO_APP
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%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %bosco to i32
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tail call i32 asm sideeffect "or $0, ${1:D}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
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ret i32 0
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}
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; In little endian the source reg will be 0 bytes into the long long
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; In big endian the source reg will be 4 bytes into the long long
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define i32 @constraint_L() nounwind {
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entry:
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; ALL-LABEL: constraint_L:
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; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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; ALL: #APP
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; LE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
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; BE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
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; ALL: #NO_APP
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%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %bosco to i32
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tail call i32 asm sideeffect "or $0, ${1:L}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
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ret i32 0
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}
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; In little endian the source reg will be 4 bytes into the long long
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; In big endian the source reg will be 0 bytes into the long long
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define i32 @constraint_M() nounwind {
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entry:
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; ALL-LABEL: constraint_M:
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; ALL: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
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; ALL: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
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; ALL: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
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; ALL: #APP
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; LE32: or ${{[0-9]+}}, $[[SECOND]], ${{[0-9]+}}
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; BE32: or ${{[0-9]+}}, $[[FIRST]], ${{[0-9]+}}
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; ALL: #NO_APP
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%bosco = load i64, i64* getelementptr inbounds (%union.u_tag, %union.u_tag* @uval, i32 0, i32 0), align 8
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%trunc1 = trunc i64 %bosco to i32
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tail call i32 asm sideeffect "or $0, ${1:M}, $2", "=r,r,r"(i64 %bosco, i32 %trunc1) nounwind
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ret i32 0
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}
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