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9d88bde411
INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags. This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg. One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input. Differential Revision: https://reviews.llvm.org/D61472 llvm-svn: 361691
268 lines
7.7 KiB
LLVM
268 lines
7.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X64
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; Check that under certain conditions we can factor out a rotate
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; from the following idioms:
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; (a*c0) >> s1 | (a*c1)
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; (a/c0) << s1 | (a/c1)
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; This targets cases where instcombine has folded a shl/srl/mul/udiv
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; with one of the shifts from the rotate idiom
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define i64 @rolq_extract_shl(i64 %i) nounwind {
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; X86-LABEL: rolq_extract_shl:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: leal (,%edx,8), %eax
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; X86-NEXT: shldl $10, %ecx, %edx
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; X86-NEXT: shll $10, %ecx
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; X86-NEXT: shrl $25, %eax
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; X86-NEXT: orl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: rolq_extract_shl:
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; X64: # %bb.0:
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; X64-NEXT: leaq (,%rdi,8), %rax
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; X64-NEXT: rolq $7, %rax
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; X64-NEXT: retq
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%lhs_mul = shl i64 %i, 3
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%rhs_mul = shl i64 %i, 10
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%lhs_shift = lshr i64 %lhs_mul, 57
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%out = or i64 %lhs_shift, %rhs_mul
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ret i64 %out
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}
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define i16 @rolw_extract_shrl(i16 %i) nounwind {
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; X86-LABEL: rolw_extract_shrl:
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; X86: # %bb.0:
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; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: shrl $3, %eax
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; X86-NEXT: rolw $12, %ax
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: rolw_extract_shrl:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %di, %eax
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; X64-NEXT: shrl $3, %eax
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; X64-NEXT: rolw $12, %ax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%lhs_div = lshr i16 %i, 7
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%rhs_div = lshr i16 %i, 3
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%rhs_shift = shl i16 %rhs_div, 12
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%out = or i16 %lhs_div, %rhs_shift
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ret i16 %out
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}
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define i32 @roll_extract_mul(i32 %i) nounwind {
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; X86-LABEL: roll_extract_mul:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: leal (%eax,%eax,8), %eax
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; X86-NEXT: roll $7, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: roll_extract_mul:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal (%rdi,%rdi,8), %eax
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; X64-NEXT: roll $7, %eax
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; X64-NEXT: retq
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%lhs_mul = mul i32 %i, 9
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%rhs_mul = mul i32 %i, 1152
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%lhs_shift = lshr i32 %lhs_mul, 25
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%out = or i32 %lhs_shift, %rhs_mul
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ret i32 %out
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}
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define i8 @rolb_extract_udiv(i8 %i) nounwind {
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; X86-LABEL: rolb_extract_udiv:
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; X86: # %bb.0:
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: imull $171, %eax, %eax
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; X86-NEXT: shrl $9, %eax
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; X86-NEXT: rolb $4, %al
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: rolb_extract_udiv:
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; X64: # %bb.0:
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: imull $171, %eax, %eax
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; X64-NEXT: shrl $9, %eax
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; X64-NEXT: rolb $4, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%lhs_div = udiv i8 %i, 3
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%rhs_div = udiv i8 %i, 48
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%lhs_shift = shl i8 %lhs_div, 4
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%out = or i8 %lhs_shift, %rhs_div
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ret i8 %out
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}
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define i64 @rolq_extract_mul_with_mask(i64 %i) nounwind {
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; X86-LABEL: rolq_extract_mul_with_mask:
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; X86: # %bb.0:
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; X86-NEXT: pushl %esi
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: shll $7, %ecx
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; X86-NEXT: leal (%ecx,%ecx,8), %ecx
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; X86-NEXT: movl $9, %edx
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; X86-NEXT: mull %edx
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; X86-NEXT: leal (%esi,%esi,8), %eax
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; X86-NEXT: addl %edx, %eax
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; X86-NEXT: movzbl %cl, %ecx
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; X86-NEXT: shrl $25, %eax
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; X86-NEXT: orl %ecx, %eax
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: popl %esi
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; X86-NEXT: retl
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;
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; X64-LABEL: rolq_extract_mul_with_mask:
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; X64: # %bb.0:
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; X64-NEXT: leaq (%rdi,%rdi,8), %rax
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; X64-NEXT: rolq $7, %rax
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; X64-NEXT: movzbl %al, %eax
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; X64-NEXT: retq
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%lhs_mul = mul i64 %i, 1152
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%rhs_mul = mul i64 %i, 9
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%lhs_and = and i64 %lhs_mul, 160
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%rhs_shift = lshr i64 %rhs_mul, 57
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%out = or i64 %lhs_and, %rhs_shift
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ret i64 %out
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}
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; Result would undershift
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define i64 @no_extract_shl(i64 %i) nounwind {
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; X86-LABEL: no_extract_shl:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X86-NEXT: movl %edx, %eax
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; X86-NEXT: shll $5, %eax
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; X86-NEXT: shldl $10, %ecx, %edx
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; X86-NEXT: shll $10, %ecx
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; X86-NEXT: shrl $25, %eax
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; X86-NEXT: orl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: no_extract_shl:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: shlq $5, %rax
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; X64-NEXT: shlq $10, %rdi
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; X64-NEXT: shrq $57, %rax
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; X64-NEXT: addq %rdi, %rax
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; X64-NEXT: retq
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%lhs_mul = shl i64 %i, 5
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%rhs_mul = shl i64 %i, 10
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%lhs_shift = lshr i64 %lhs_mul, 57
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%out = or i64 %lhs_shift, %rhs_mul
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ret i64 %out
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}
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; Result would overshift
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define i32 @no_extract_shrl(i32 %i) nounwind {
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; X86-LABEL: no_extract_shrl:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl %eax, %ecx
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; X86-NEXT: andl $-8, %ecx
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; X86-NEXT: shll $25, %ecx
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; X86-NEXT: shrl $9, %eax
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; X86-NEXT: orl %ecx, %eax
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; X86-NEXT: retl
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;
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; X64-LABEL: no_extract_shrl:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: andl $-8, %eax
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; X64-NEXT: shll $25, %eax
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; X64-NEXT: shrl $9, %edi
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; X64-NEXT: addl %edi, %eax
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; X64-NEXT: retq
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%lhs_div = lshr i32 %i, 3
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%rhs_div = lshr i32 %i, 9
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%lhs_shift = shl i32 %lhs_div, 28
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%out = or i32 %lhs_shift, %rhs_div
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ret i32 %out
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}
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; Can factor 128 from 2304, but result is 18 instead of 9
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define i16 @no_extract_mul(i16 %i) nounwind {
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; X86-LABEL: no_extract_mul:
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; X86: # %bb.0:
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: leal (%eax,%eax,8), %ecx
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; X86-NEXT: shll $8, %eax
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; X86-NEXT: leal (%eax,%eax,8), %edx
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; X86-NEXT: movzwl %cx, %eax
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; X86-NEXT: shrl $9, %eax
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; X86-NEXT: orl %edx, %eax
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; X86-NEXT: # kill: def $ax killed $ax killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: no_extract_mul:
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; X64: # %bb.0:
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; X64-NEXT: # kill: def $edi killed $edi def $rdi
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; X64-NEXT: leal (%rdi,%rdi,8), %eax
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; X64-NEXT: # kill: def $edi killed $edi killed $rdi def $rdi
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; X64-NEXT: shll $8, %edi
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; X64-NEXT: leal (%rdi,%rdi,8), %ecx
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; X64-NEXT: movzwl %ax, %eax
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; X64-NEXT: shrl $9, %eax
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; X64-NEXT: orl %ecx, %eax
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; X64-NEXT: # kill: def $ax killed $ax killed $eax
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; X64-NEXT: retq
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%lhs_mul = mul i16 %i, 2304
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%rhs_mul = mul i16 %i, 9
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%rhs_shift = lshr i16 %rhs_mul, 9
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%out = or i16 %lhs_mul, %rhs_shift
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ret i16 %out
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}
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; Can't evenly factor 16 from 49
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define i8 @no_extract_udiv(i8 %i) nounwind {
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; X86-LABEL: no_extract_udiv:
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; X86: # %bb.0:
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; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: imull $171, %eax, %ecx
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; X86-NEXT: shlb $3, %ch
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; X86-NEXT: andb $-16, %ch
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; X86-NEXT: imull $79, %eax, %edx
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; X86-NEXT: subb %dh, %al
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; X86-NEXT: shrb %al
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; X86-NEXT: addb %dh, %al
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; X86-NEXT: shrb $5, %al
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; X86-NEXT: orb %ch, %al
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; X86-NEXT: # kill: def $al killed $al killed $eax
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; X86-NEXT: retl
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;
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; X64-LABEL: no_extract_udiv:
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; X64: # %bb.0:
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: imull $171, %eax, %ecx
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; X64-NEXT: shrl $8, %ecx
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; X64-NEXT: shlb $3, %cl
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; X64-NEXT: andb $-16, %cl
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; X64-NEXT: imull $79, %eax, %edx
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; X64-NEXT: shrl $8, %edx
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; X64-NEXT: subb %dl, %al
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; X64-NEXT: shrb %al
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; X64-NEXT: addb %dl, %al
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; X64-NEXT: shrb $5, %al
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; X64-NEXT: orb %cl, %al
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; X64-NEXT: # kill: def $al killed $al killed $eax
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; X64-NEXT: retq
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%lhs_div = udiv i8 %i, 3
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%rhs_div = udiv i8 %i, 49
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%lhs_shift = shl i8 %lhs_div,4
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%out = or i8 %lhs_shift, %rhs_div
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ret i8 %out
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}
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