Sander de Smalen a1e07e5345 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support ...

Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D40360

llvm-svn: 319315

2017-11-29 14:34:18 +00:00

..

AArch64

[AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support

2017-11-29 14:34:18 +00:00

AMDGPU

AMDGPU: Add num spilled s/vgprs to metadata

2017-11-28 17:51:08 +00:00

ARM

[ARM] Add support for armv7e-m to the .arch directive

2017-11-29 10:12:15 +00:00

AsmParser

[MC] Fix regression tests on Windows when git “core.autocrlf” is set to true.

2017-11-17 21:59:43 +00:00

AVR

[AVR] Use the short form of 'clr <reg>'

2017-11-24 15:36:43 +00:00

BPF

bpf: print backward branch target properly

2017-11-16 19:15:36 +00:00

COFF

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00

Disassembler

[AMDGPU][MC][DISASSEMBLER][GFX9] Corrected decoding of GLOBAL/SCRATCH opcodes

2017-11-27 17:14:35 +00:00

ELF

[DWARF] Fix handling of extended line-number opcodes

2017-11-22 15:14:49 +00:00

Hexagon

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

Lanai

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MachO

[dwarfdump] Add verbose output for .debug-line section

2017-09-21 20:15:30 +00:00

Markup

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Mips

[mips] Set microMIPS ASE flag

2017-11-24 14:00:47 +00:00

PowerPC

PowerPC: support the separator character in the IAS

2017-10-24 16:19:56 +00:00

RISCV

[RISCV] MC layer support for the standard RV32A instruction set extension

2017-11-09 15:00:03 +00:00

Sparc

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SystemZ

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WebAssembly

[WebAssembly] MC: Don't allow zero sized data segments

2017-10-27 00:08:55 +00:00

X86

[CodeGen] Print register names in lowercase in both MIR and debug output

2017-11-28 17:15:09 +00:00