Alex Bradbury a1e9486b88 [RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention ...

When an instruction mnemonic contains a '.', we usually name the instruction
with a _ in that place. e.g. fadd.s -> FADD_S.

This patch updates RISCVInstrInfoC.td to do the same, e.g. c.nop -> C_NOP.

Also includes some minor formatting changes in RISCVInstrInfoC.td to better
align it with the formatting conventions in the rest of the backend.

llvm-svn: 320560

2017-12-13 09:57:25 +00:00

..

AsmParser

[RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted position

2017-12-13 09:41:21 +00:00

Disassembler

[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention

2017-12-13 09:57:25 +00:00

InstPrinter

[RISCV] Implement assembler pseudo instructions for RV32I and RV64I

2017-12-12 15:46:15 +00:00

MCTargetDesc

[RISCV] MC layer support for the jump/branch instructions of the RVC extension

2017-12-07 13:19:57 +00:00

TargetInfo

Fix RISCV build after r318352

2017-11-16 18:39:31 +00:00

CMakeLists.txt

[RISCV] Add custom CC_RISCV calling convention and improved call support

2017-12-11 12:49:02 +00:00

LLVMBuild.txt

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCV.h

[RISCV] Codegen support for memory operations on global addresses

2017-11-08 13:24:21 +00:00

RISCV.td

[RISCV] Implement assembler pseudo instructions for RV32I and RV64I

2017-12-12 15:46:15 +00:00

RISCVAsmPrinter.cpp

[RISCV] Codegen support for memory operations on global addresses

2017-11-08 13:24:21 +00:00

RISCVCallingConv.td

[RISCV] Add custom CC_RISCV calling convention and improved call support

2017-12-11 12:49:02 +00:00

RISCVFrameLowering.cpp

[RISCV] Implement prolog and epilog insertion

2017-12-11 12:34:11 +00:00

RISCVFrameLowering.h

[RISCV] Implement prolog and epilog insertion

2017-12-11 12:34:11 +00:00

RISCVInstrFormats.td

[RISCV] MC layer support for load/store instructions of the C (compressed) extension

2017-12-07 12:50:32 +00:00

RISCVInstrFormatsC.td

[RISCV] MC layer support for the remaining RVC instructions

2017-12-13 09:32:55 +00:00

RISCVInstrInfo.cpp

[RISCV][NFC] Use TargetRegisterClass::hasSubClassEq in storeRegToStackSlot/loadReadFromStackSlot

2017-12-07 12:45:05 +00:00

RISCVInstrInfo.h

[RISCV] Codegen for conditional branches

2017-11-08 13:31:40 +00:00

RISCVInstrInfo.td

[RISCV][NFC] Formatting fix in RISCVInstrInfo.td

2017-12-12 16:10:21 +00:00

RISCVInstrInfoA.td

[RISCV] MC layer support for the standard RV64A instruction set extension

2017-12-07 10:59:12 +00:00

RISCVInstrInfoC.td

[RISCV][NFC] Update RISCVInstrInfoC.td to match usual instruction naming convention

2017-12-13 09:57:25 +00:00

RISCVInstrInfoD.td

[RISCV] MC layer support for the standard RV64D instruction set extension

2017-12-07 11:04:18 +00:00

RISCVInstrInfoF.td

[RISCV] MC layer support for the standard RV64F instruction set extension

2017-12-07 11:02:55 +00:00

RISCVInstrInfoM.td

[RISCV] MC layer support for the standard RV64M instruction set extension

2017-12-07 10:56:07 +00:00

RISCVISelDAGToDAG.cpp

[RISCV] Support lowering FrameIndex

2017-12-11 11:53:54 +00:00

RISCVISelLowering.cpp

[RISCV] Add custom CC_RISCV calling convention and improved call support

2017-12-11 12:49:02 +00:00

RISCVISelLowering.h

[RISCV] Add custom CC_RISCV calling convention and improved call support

2017-12-11 12:49:02 +00:00

RISCVMCInstLower.cpp

[RISCV] Support and tests for a variety of additional LLVM IR constructs

2017-11-21 08:11:03 +00:00

RISCVRegisterInfo.cpp

[RISCV] Support lowering FrameIndex

2017-12-11 11:53:54 +00:00

RISCVRegisterInfo.h

Fix a bunch more layering of CodeGen headers that are in Target

2017-11-17 01:07:10 +00:00

RISCVRegisterInfo.td

[RISCV] MC layer support for the remaining RVC instructions

2017-12-13 09:32:55 +00:00

RISCVSubtarget.cpp

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00

RISCVSubtarget.h

[RISCV] MC layer support for load/store instructions of the C (compressed) extension

2017-12-07 12:50:32 +00:00

RISCVTargetMachine.cpp

[RISCV] Fix 64-bit data layout mismatch between backend and target description

2017-11-16 20:30:49 +00:00

RISCVTargetMachine.h

[RISCV] Initial codegen support for ALU operations

2017-10-19 21:37:38 +00:00