llvm-mirror/lib/CodeGen
Nadav Rotem edd576d454 Fix a typo in the comment.
llvm-svn: 163496
2012-09-10 08:51:46 +00:00
..
AsmPrinter Fix alignment of .comm and .lcomm on mingw32. 2012-09-07 21:08:01 +00:00
SelectionDAG Teach the DAGBuilder about lifetime markers which are generated from PHINodes. 2012-09-10 08:43:23 +00:00
AggressiveAntiDepBreaker.cpp
AggressiveAntiDepBreaker.h
AllocationOrder.cpp
AllocationOrder.h
Analysis.cpp
AntiDepBreaker.h
BranchFolding.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
BranchFolding.h
CalcSpillWeights.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
CallingConvLower.cpp Add an ensureMaxAlignment() function to MachineFrameInfo (analogous to 2012-06-19 22:59:12 +00:00
CMakeLists.txt Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be 2012-09-06 09:17:37 +00:00
CodeGen.cpp Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be 2012-09-06 09:17:37 +00:00
CodePlacementOpt.cpp
CriticalAntiDepBreaker.cpp
CriticalAntiDepBreaker.h
DeadMachineInstructionElim.cpp
DFAPacketizer.cpp Revert r158679 - use case is unclear (and it increases the memory footprint). 2012-06-22 20:27:13 +00:00
DwarfEHPrepare.cpp
EarlyIfConversion.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
EdgeBundles.cpp
ExecutionDepsFix.cpp
ExpandISelPseudos.cpp
ExpandPostRAPseudos.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
GCMetadata.cpp
GCMetadataPrinter.cpp
GCStrategy.cpp
IfConversion.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
InlineSpiller.cpp Fix typo. 2012-09-01 12:11:41 +00:00
InterferenceCache.cpp Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
InterferenceCache.h Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
IntrinsicLowering.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
JITCodeEmitter.cpp
LatencyPriorityQueue.cpp
LexicalScopes.cpp Move lib/Analysis/DebugInfo.cpp to lib/VMCore/DebugInfo.cpp and 2012-06-28 00:05:13 +00:00
LiveDebugVariables.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
LiveDebugVariables.h
LiveInterval.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
LiveIntervalAnalysis.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
LiveIntervalUnion.cpp
LiveIntervalUnion.h
LiveRangeCalc.cpp Clear kill flags while computing live ranges. 2012-09-06 18:15:15 +00:00
LiveRangeCalc.h Be more verbose when detecting dominance problems. 2012-07-13 23:39:05 +00:00
LiveRangeEdit.cpp Avoid creating dangling physreg live ranges during DCE. 2012-08-02 16:36:47 +00:00
LiveRegMatrix.cpp Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
LiveRegMatrix.h Convert RAGreedy to LiveRegMatrix interference checking. 2012-06-20 22:52:26 +00:00
LiveStackAnalysis.cpp
LiveVariables.cpp LiveVariables: Compute a set of defs and kills to speed up updating LV during critical edge splitting. 2012-09-09 11:56:14 +00:00
LLVMBuild.txt
LLVMTargetMachine.cpp Extend TargetPassConfig to allow running only a subset of the normal passes. 2012-07-02 19:48:45 +00:00
LocalStackSlotAllocation.cpp
MachineBasicBlock.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
MachineBlockFrequencyInfo.cpp
MachineBlockPlacement.cpp Add a much more conservative strategy for aligning branch targets. 2012-08-07 09:45:24 +00:00
MachineBranchProbabilityInfo.cpp Fix a quadratic algorithm in MachineBranchProbabilityInfo. 2012-08-20 22:01:38 +00:00
MachineCodeEmitter.cpp
MachineCopyPropagation.cpp
MachineCSE.cpp MachineCSE: Hoist isConstantPhysReg out of the loop, it checks for overlaps already. 2012-08-11 20:42:59 +00:00
MachineDominators.cpp
MachineFunction.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
MachineFunctionAnalysis.cpp
MachineFunctionPass.cpp
MachineFunctionPrinterPass.cpp Print SlotIndexes when available for -print-machineinstrs. 2012-07-04 23:53:19 +00:00
MachineInstr.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
MachineInstrBundle.cpp
MachineLICM.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
MachineLoopInfo.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
MachineLoopRanges.cpp
MachineModuleInfo.cpp
MachineModuleInfoImpls.cpp
MachinePassRegistry.cpp
MachineRegisterInfo.cpp Reapply r161633-161634 "Partition use lists so defs always come before uses."" 2012-08-10 00:21:30 +00:00
MachineScheduler.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
MachineSink.cpp MachineSink: Sort the successors before trying to find SuccToSinkTo. 2012-07-31 20:45:38 +00:00
MachineSSAUpdater.cpp Fix undefined behavior: binding null pointer to reference. No functionality change. 2012-08-14 05:31:26 +00:00
MachineTraceMetrics.cpp Give MachineTraceMetrics its own debug tag. 2012-08-10 22:27:29 +00:00
MachineTraceMetrics.h Add more trace query functions. 2012-08-10 22:27:27 +00:00
MachineVerifier.cpp Stop casting away const qualifier needlessly. 2012-09-05 22:26:57 +00:00
Makefile
OcamlGC.cpp
OptimizePHIs.cpp
Passes.cpp Add a new optimization pass: Stack Coloring, that merges disjoint static allocations (allocas). Allocas are known to be 2012-09-06 09:17:37 +00:00
PeepholeOptimizer.cpp Use standard pattern for iterate+erase. 2012-08-17 14:38:59 +00:00
PHIElimination.cpp Split loop exiting edges more aggressively. 2012-07-20 20:49:53 +00:00
PHIEliminationUtils.cpp
PHIEliminationUtils.h
PostRASchedulerList.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
ProcessImplicitDefs.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
PrologEpilogInserter.cpp
PrologEpilogInserter.h
PseudoSourceValue.cpp
README.txt
RegAllocBase.cpp Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBase.h Remove LiveIntervalUnions from RegAllocBase. 2012-06-20 22:52:29 +00:00
RegAllocBasic.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocFast.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocGreedy.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegAllocPBQP.cpp Remove unused typedefs gcc4.8 warns about. 2012-09-05 17:55:46 +00:00
RegisterClassInfo.cpp
RegisterCoalescer.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
RegisterCoalescer.h Allow overlaps between virtreg and physreg live ranges. 2012-09-06 18:15:23 +00:00
RegisterPressure.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
RegisterScavenging.cpp
ScheduleDAG.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
ScheduleDAGInstrs.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
ScheduleDAGPrinter.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
ScoreboardHazardRecognizer.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
ShadowStackGC.cpp Move llvm/Support/IRBuilder.h -> llvm/IRBuilder.h 2012-06-29 12:38:19 +00:00
ShrinkWrapping.cpp Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed. 2012-08-22 06:07:19 +00:00
SjLjEHPrepare.cpp IRBuilderify the SjlLjEHPrepare pass. 2012-09-03 12:27:43 +00:00
SlotIndexes.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
Spiller.cpp
Spiller.h
SpillPlacement.cpp
SpillPlacement.h
SplitKit.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
SplitKit.h
StackColoring.cpp Fix a typo in the comment. 2012-09-10 08:51:46 +00:00
StackProtector.cpp Add support for the --param ssp-buffer-size= driver option. 2012-08-21 16:15:24 +00:00
StackSlotColoring.cpp Tidy up a few more uses of MF.getFunction()->getName(). 2012-08-22 17:18:53 +00:00
StrongPHIElimination.cpp Reduce duplicated hash map lookups. 2012-08-22 15:37:57 +00:00
TailDuplication.cpp
TargetFrameLoweringImpl.cpp
TargetInstrInfoImpl.cpp Use CloneMachineInstr to make a new MI in commuteInstruction to make the code tolerant of instructions with more than two input operands. 2012-08-31 16:30:05 +00:00
TargetLoweringObjectFileImpl.cpp Remove tabs. 2012-07-19 00:04:14 +00:00
TargetOptionsImpl.cpp
TwoAddressInstructionPass.cpp Search the whole instruction for tied operands. 2012-09-04 22:59:30 +00:00
UnreachableBlockElim.cpp
VirtRegMap.cpp Release build: guard dump functions with "ifndef NDEBUG" 2012-09-06 19:06:06 +00:00
VirtRegMap.h

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelihood the store may become dead.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
        ldr r3, [sp, #+4]
        add r3, r3, #3
        ldr r2, [sp, #+8]
        add r2, r2, #2
        ldr r1, [sp, #+4]  <==
        add r1, r1, #1
        ldr r0, [sp, #+4]
        add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//

It's not always a good idea to choose rematerialization over spilling. If all
the load / store instructions would be folded then spilling is cheaper because
it won't require new live intervals / registers. See 2003-05-31-LongShifts for
an example.

//===---------------------------------------------------------------------===//

With a copying garbage collector, derived pointers must not be retained across
collector safe points; the collector could move the objects and invalidate the
derived pointer. This is bad enough in the first place, but safe points can
crop up unpredictably. Consider:

        %array = load { i32, [0 x %obj] }** %array_addr
        %nth_el = getelementptr { i32, [0 x %obj] }* %array, i32 0, i32 %n
        %old = load %obj** %nth_el
        %z = div i64 %x, %y
        store %obj* %new, %obj** %nth_el

If the i64 division is lowered to a libcall, then a safe point will (must)
appear for the call site. If a collection occurs, %array and %nth_el no longer
point into the correct object.

The fix for this is to copy address calculations so that dependent pointers
are never live across safe point boundaries. But the loads cannot be copied
like this if there was an intervening store, so may be hard to get right.

Only a concurrent mutator can trigger a collection at the libcall safe point.
So single-threaded programs do not have this requirement, even with a copying
collector. Still, LLVM optimizations would probably undo a front-end's careful
work.

//===---------------------------------------------------------------------===//

The ocaml frametable structure supports liveness information. It would be good
to support it.

//===---------------------------------------------------------------------===//

The FIXME in ComputeCommonTailLength in BranchFolding.cpp needs to be
revisited. The check is there to work around a misuse of directives in inline
assembly.

//===---------------------------------------------------------------------===//

It would be good to detect collector/target compatibility instead of silently
doing the wrong thing.

//===---------------------------------------------------------------------===//

It would be really nice to be able to write patterns in .td files for copies,
which would eliminate a bunch of explicit predicates on them (e.g. no side 
effects).  Once this is in place, it would be even better to have tblgen 
synthesize the various copy insertion/inspection methods in TargetInstrInfo.

//===---------------------------------------------------------------------===//

Stack coloring improvements:

1. Do proper LiveStackAnalysis on all stack objects including those which are
   not spill slots.
2. Reorder objects to fill in gaps between objects.
   e.g. 4, 1, <gap>, 4, 1, 1, 1, <gap>, 4 => 4, 1, 1, 1, 1, 4, 4

//===---------------------------------------------------------------------===//

The scheduler should be able to sort nearby instructions by their address. For
example, in an expanded memset sequence it's not uncommon to see code like this:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

Each of the stores is independent, and the scheduler is currently making an
arbitrary decision about the order.

//===---------------------------------------------------------------------===//

Another opportunitiy in this code is that the $0 could be moved to a register:

  movl $0, 4(%rdi)
  movl $0, 8(%rdi)
  movl $0, 12(%rdi)
  movl $0, 0(%rdi)

This would save substantial code size, especially for longer sequences like
this. It would be easy to have a rule telling isel to avoid matching MOV32mi
if the immediate has more than some fixed number of uses. It's more involved
to teach the register allocator how to do late folding to recover from
excessive register pressure.