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a4bd7d9c3c
Add VEX_LIG to scalar FMA4 instructions. Use VEX_LIG in some of the inheriting checks in disassembler table generator. Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts. Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set. Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases. Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms. llvm-svn: 191649 |
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| check-each-file | ||
| clang-parse-diagnostics-file | ||
| codegen-diff | ||
| countloc.sh | ||
| DSAclean.py | ||
| DSAextract.py | ||
| findmisopt | ||
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| findsym.pl | ||
| GenLibDeps.pl | ||
| GetRepositoryPath | ||
| GetSourceVersion | ||
| getsrcs.sh | ||
| lldbDataFormatters.py | ||
| llvm-compilers-check | ||
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| llvm.grm | ||
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| LLVMBuild.txt | ||
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| Makefile | ||
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| profile.pl | ||
| sort_includes.py | ||
| test_debuginfo.pl | ||
| UpdateCMakeLists.pl | ||
| wciia.py | ||