Evan Cheng ae2915ac91 Oops. Typo. ... llvm-svn: 25260		2006-01-13 01:06:49 +00:00
..
Alpha	Add bswap, rotl, and rotr nodes	2006-01-11 21:21:00 +00:00
CBackend	yet more C++ standards-compliance stuff.	2005-12-27 10:40:34 +00:00
IA64	sabre's (correct) fix means these guys need to be flagged as well (else	2006-01-12 03:28:40 +00:00
PowerPC	ahem :)	2006-01-12 02:05:36 +00:00
Skeleton	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
SparcV8	Fix branches on FP compares	2006-01-12 17:05:32 +00:00
SparcV9	Support multiple ValueTypes per RegisterClass, needed for upcoming vector	2005-12-01 04:51:06 +00:00
X86	Oops. Typo.	2006-01-13 01:06:49 +00:00
Makefile	DONT_BUILD_RELINKED is gone and implied by BUILD_ARCHIVE now	2005-10-24 02:26:13 +00:00
MRegisterInfo.cpp	Rename MRegisterDesc -> TargetRegisterDesc for consistency	2005-09-30 17:49:27 +00:00
SubtargetFeature.cpp	Preparation of supporting scheduling info. Need to find info based on selected	2005-10-25 15:15:28 +00:00
Target.td	New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace	2006-01-09 18:28:21 +00:00
TargetData.cpp	Update to use the new MathExtras.h support for log2 computation.	2005-08-02 19:26:06 +00:00
TargetFrameInfo.cpp	Eliminate all remaining tabs and trailing spaces.	2005-07-27 06:12:32 +00:00
TargetInstrInfo.cpp	Convert tabs to spaces	2005-04-22 17:54:37 +00:00
TargetLowering.cpp	Lefted out TargetLowering::	2005-12-21 23:14:54 +00:00
TargetMachine.cpp	Remove the X86 and PowerPC Simple instruction selectors; their time has	2005-08-18 23:53:15 +00:00
TargetMachineRegistry.cpp	1. Use SubtargetFeatures in llc/lli.	2005-09-01 21:38:21 +00:00
TargetSchedInfo.cpp	Convert tabs to spaces	2005-04-22 17:54:37 +00:00
TargetSchedule.td	add a marker	2005-10-23 22:07:20 +00:00
TargetSelectionDAG.td	Add bswap, rotl, and rotr nodes	2006-01-11 21:21:00 +00:00
TargetSubtarget.cpp	Eliminate all remaining tabs and trailing spaces.	2005-07-27 06:12:32 +00:00