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d64e304671
the overloaded vector types allowed floating-point or integer vector elements. Most of these operations actually depend on the element type, so bitcasting was not an option. If you include the vpadd intrinsics that I updated earlier, this gets rid of 20 intrinsics. llvm-svn: 78646
34 lines
1.2 KiB
LLVM
34 lines
1.2 KiB
LLVM
; RUN: llvm-as < %s | llc -march=arm -mattr=+neon > %t
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; RUN: grep {vrsqrte\\.u32} %t | count 2
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; RUN: grep {vrsqrte\\.f32} %t | count 2
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define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
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ret <2 x i32> %tmp2
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}
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define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
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ret <4 x i32> %tmp2
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}
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define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
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ret <2 x float> %tmp2
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}
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define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
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ret <4 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32>) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32>) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
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