mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-06 03:08:43 +00:00
9aad2bbcf9
#NAME# with the name of the defm instantiating the multiclass. This is useful for AVX instruction naming where a "V" prefix is standard throughout the ISA. For example: multiclass SSE_AVX_Inst<...> { def SS : Instr<...>; def SD : Instr<...>; def PS : Instr<...>; def PD : Instr<...>; def V#NAME#SS : Instr<...>; def V#NAME#SD : Instr<...>; def V#NAME#PS : Instr<...>; def V#NAME#PD : Instr<...>; } defm ADD : SSE_AVX_Inst<...>; Results in ADDSS ADDSD ADDPS ADDPD VADDSS VADDSD VADDPS VADDPD llvm-svn: 70979 |
||
---|---|---|
.. | ||
2003-08-03-PassCode.td | ||
2006-09-18-LargeInt.td | ||
AnonDefinitionOnDemand.td | ||
BitsInitOverflow.td | ||
CStyleComment.td | ||
DagDefSubst.ll | ||
DagIntSubst.ll | ||
DefmInherit.td | ||
dg.exp | ||
ForwardRef.td | ||
GeneralList.td | ||
Include.inc | ||
Include.td | ||
IntBitInit.td | ||
LazyChange.td | ||
ListConversion.td | ||
ListSlices.td | ||
MultiClass.td | ||
MultiClassDefName.td | ||
MultiClassInherit.td | ||
nameconcat.td | ||
nested-comment.td | ||
strconcat.td | ||
String.td | ||
SuperSubclassSameName.td | ||
TargetInstrInfo.td | ||
TemplateArgRename.td | ||
Tree.td | ||
TreeNames.td | ||
UnterminatedComment.td |