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1ae2a5de8f
We would like to split the SP adjustment to reduce the instructions in
prologue and epilogue as the following case. In this way, the offset of
the callee saved register could fit in a single store.
add sp,sp,-2032
sw ra,2028(sp)
sw s0,2024(sp)
sw s1,2020(sp)
sw s3,2012(sp)
sw s4,2008(sp)
add sp,sp,-64
Differential Revision: https://reviews.llvm.org/D68011
llvm-svn: 373688
161 lines
7.5 KiB
LLVM
161 lines
7.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
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; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
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; TODO: the quality of the generated code is poor
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define void @test() {
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; RV32I-FPELIM-LABEL: test:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: lui a0, 74565
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; RV32I-FPELIM-NEXT: addi a0, a0, 1664
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; RV32I-FPELIM-NEXT: sub sp, sp, a0
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 305419904
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; RV32I-FPELIM-NEXT: lui a0, 74565
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; RV32I-FPELIM-NEXT: addi a0, a0, 1664
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; RV32I-FPELIM-NEXT: add sp, sp, a0
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: test:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-WITHFP-NEXT: sw ra, 2028(sp)
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; RV32I-WITHFP-NEXT: sw s0, 2024(sp)
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; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32I-WITHFP-NEXT: addi s0, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32I-WITHFP-NEXT: lui a0, 74565
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; RV32I-WITHFP-NEXT: addi a0, a0, -352
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; RV32I-WITHFP-NEXT: sub sp, sp, a0
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 305419920
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; RV32I-WITHFP-NEXT: lui a0, 74565
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; RV32I-WITHFP-NEXT: addi a0, a0, -352
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; RV32I-WITHFP-NEXT: add sp, sp, a0
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
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; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 305419920
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; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
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; RV32I-WITHFP-NEXT: .cfi_restore ra
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; RV32I-WITHFP-NEXT: .cfi_restore s0
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; RV32I-WITHFP-NEXT: addi sp, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32I-WITHFP-NEXT: ret
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%tmp = alloca [ 305419896 x i8 ] , align 4
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ret void
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}
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; This test case artificially produces register pressure which should force
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; use of the emergency spill slot.
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define void @test_emergency_spill_slot(i32 %a) {
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; RV32I-FPELIM-LABEL: test_emergency_spill_slot:
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; RV32I-FPELIM: # %bb.0:
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; RV32I-FPELIM-NEXT: addi sp, sp, -2032
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-FPELIM-NEXT: sw s0, 2028(sp)
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; RV32I-FPELIM-NEXT: sw s1, 2024(sp)
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; RV32I-FPELIM-NEXT: .cfi_offset s0, -4
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; RV32I-FPELIM-NEXT: .cfi_offset s1, -8
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; RV32I-FPELIM-NEXT: lui a1, 97
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; RV32I-FPELIM-NEXT: addi a1, a1, 672
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; RV32I-FPELIM-NEXT: sub sp, sp, a1
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 400016
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; RV32I-FPELIM-NEXT: lui a1, 78
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; RV32I-FPELIM-NEXT: addi a1, a1, 512
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; RV32I-FPELIM-NEXT: addi a2, sp, 8
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; RV32I-FPELIM-NEXT: add a1, a2, a1
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; RV32I-FPELIM-NEXT: #APP
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; RV32I-FPELIM-NEXT: nop
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; RV32I-FPELIM-NEXT: #NO_APP
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; RV32I-FPELIM-NEXT: sw a0, 0(a1)
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; RV32I-FPELIM-NEXT: #APP
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; RV32I-FPELIM-NEXT: nop
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; RV32I-FPELIM-NEXT: #NO_APP
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; RV32I-FPELIM-NEXT: lui a0, 97
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; RV32I-FPELIM-NEXT: addi a0, a0, 672
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; RV32I-FPELIM-NEXT: add sp, sp, a0
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-FPELIM-NEXT: lw s1, 2024(sp)
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; RV32I-FPELIM-NEXT: lw s0, 2028(sp)
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; RV32I-FPELIM-NEXT: .cfi_restore s0
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; RV32I-FPELIM-NEXT: .cfi_restore s1
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; RV32I-FPELIM-NEXT: addi sp, sp, 2032
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; RV32I-FPELIM-NEXT: .cfi_def_cfa_offset 0
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; RV32I-FPELIM-NEXT: ret
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;
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; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
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; RV32I-WITHFP: # %bb.0:
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; RV32I-WITHFP-NEXT: addi sp, sp, -2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-WITHFP-NEXT: sw ra, 2028(sp)
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; RV32I-WITHFP-NEXT: sw s0, 2024(sp)
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; RV32I-WITHFP-NEXT: sw s1, 2020(sp)
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; RV32I-WITHFP-NEXT: sw s2, 2016(sp)
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; RV32I-WITHFP-NEXT: .cfi_offset ra, -4
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; RV32I-WITHFP-NEXT: .cfi_offset s0, -8
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; RV32I-WITHFP-NEXT: .cfi_offset s1, -12
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; RV32I-WITHFP-NEXT: .cfi_offset s2, -16
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; RV32I-WITHFP-NEXT: addi s0, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa s0, 0
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; RV32I-WITHFP-NEXT: lui a1, 97
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; RV32I-WITHFP-NEXT: addi a1, a1, 688
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; RV32I-WITHFP-NEXT: sub sp, sp, a1
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 400032
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; RV32I-WITHFP-NEXT: lui a1, 78
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; RV32I-WITHFP-NEXT: addi a1, a1, 512
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; RV32I-WITHFP-NEXT: lui a2, 1048478
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; RV32I-WITHFP-NEXT: addi a2, a2, 1388
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; RV32I-WITHFP-NEXT: add a2, s0, a2
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; RV32I-WITHFP-NEXT: mv a2, a2
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; RV32I-WITHFP-NEXT: add a1, a2, a1
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; RV32I-WITHFP-NEXT: #APP
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; RV32I-WITHFP-NEXT: nop
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; RV32I-WITHFP-NEXT: #NO_APP
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; RV32I-WITHFP-NEXT: sw a0, 0(a1)
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; RV32I-WITHFP-NEXT: #APP
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; RV32I-WITHFP-NEXT: nop
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; RV32I-WITHFP-NEXT: #NO_APP
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; RV32I-WITHFP-NEXT: lui a0, 97
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; RV32I-WITHFP-NEXT: addi a0, a0, 688
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; RV32I-WITHFP-NEXT: add sp, sp, a0
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 2032
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; RV32I-WITHFP-NEXT: lw s2, 2016(sp)
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; RV32I-WITHFP-NEXT: lw s1, 2020(sp)
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; RV32I-WITHFP-NEXT: lw s0, 2024(sp)
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; RV32I-WITHFP-NEXT: .cfi_def_cfa sp, 400032
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; RV32I-WITHFP-NEXT: lw ra, 2028(sp)
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; RV32I-WITHFP-NEXT: .cfi_restore ra
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; RV32I-WITHFP-NEXT: .cfi_restore s0
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; RV32I-WITHFP-NEXT: .cfi_restore s1
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; RV32I-WITHFP-NEXT: .cfi_restore s2
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; RV32I-WITHFP-NEXT: addi sp, sp, 2032
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; RV32I-WITHFP-NEXT: .cfi_def_cfa_offset 0
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; RV32I-WITHFP-NEXT: ret
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%data = alloca [ 100000 x i32 ] , align 4
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%ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
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%1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
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%asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
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%asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
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%asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
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%asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3
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%asmresult4 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 4
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%asmresult5 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 5
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%asmresult6 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 6
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%asmresult7 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 7
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%asmresult8 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 8
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%asmresult9 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 9
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%asmresult10 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 10
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%asmresult11 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 11
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%asmresult12 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 12
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%asmresult13 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 13
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%asmresult14 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 14
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store volatile i32 %a, i32* %ptr
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tail call void asm sideeffect "nop", "r,r,r,r,r,r,r,r,r,r,r,r,r,r,r"(i32 %asmresult0, i32 %asmresult1, i32 %asmresult2, i32 %asmresult3, i32 %asmresult4, i32 %asmresult5, i32 %asmresult6, i32 %asmresult7, i32 %asmresult8, i32 %asmresult9, i32 %asmresult10, i32 %asmresult11, i32 %asmresult12, i32 %asmresult13, i32 %asmresult14)
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ret void
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}
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