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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
120 lines
4.3 KiB
C++
120 lines
4.3 KiB
C++
//===- MCSubtargetInfo.cpp - Subtarget Information ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCInstrItineraries.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MC/SubtargetFeature.h"
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#include "llvm/Support/raw_ostream.h"
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#include <algorithm>
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#include <cassert>
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#include <cstring>
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using namespace llvm;
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static FeatureBitset getFeatures(StringRef CPU, StringRef FS,
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ArrayRef<SubtargetFeatureKV> ProcDesc,
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ArrayRef<SubtargetFeatureKV> ProcFeatures) {
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SubtargetFeatures Features(FS);
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return Features.getFeatureBits(CPU, ProcDesc, ProcFeatures);
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}
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void MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
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FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
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if (!CPU.empty())
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CPUSchedModel = &getSchedModelForCPU(CPU);
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else
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CPUSchedModel = &MCSchedModel::GetDefaultSchedModel();
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}
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void MCSubtargetInfo::setDefaultFeatures(StringRef CPU, StringRef FS) {
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FeatureBits = getFeatures(CPU, FS, ProcDesc, ProcFeatures);
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}
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MCSubtargetInfo::MCSubtargetInfo(
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const Triple &TT, StringRef C, StringRef FS,
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ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD,
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const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: TargetTriple(TT), CPU(C), ProcFeatures(PF), ProcDesc(PD),
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ProcSchedModels(ProcSched), WriteProcResTable(WPR), WriteLatencyTable(WL),
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ReadAdvanceTable(RA), Stages(IS), OperandCycles(OC), ForwardingPaths(FP) {
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InitMCProcessorInfo(CPU, FS);
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(uint64_t FB) {
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FeatureBits.flip(FB);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(const FeatureBitset &FB) {
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FeatureBits ^= FB;
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ToggleFeature(StringRef FS) {
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SubtargetFeatures::ToggleFeature(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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FeatureBitset MCSubtargetInfo::ApplyFeatureFlag(StringRef FS) {
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SubtargetFeatures::ApplyFeatureFlag(FeatureBits, FS, ProcFeatures);
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return FeatureBits;
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}
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bool MCSubtargetInfo::checkFeatures(StringRef FS) const {
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SubtargetFeatures T(FS);
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FeatureBitset Set, All;
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for (std::string F : T.getFeatures()) {
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SubtargetFeatures::ApplyFeatureFlag(Set, F, ProcFeatures);
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if (F[0] == '-')
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F[0] = '+';
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SubtargetFeatures::ApplyFeatureFlag(All, F, ProcFeatures);
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}
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return (FeatureBits & All) == Set;
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}
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const MCSchedModel &MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const {
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assert(ProcSchedModels && "Processor machine model not available!");
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ArrayRef<SubtargetInfoKV> SchedModels(ProcSchedModels, ProcDesc.size());
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assert(std::is_sorted(SchedModels.begin(), SchedModels.end(),
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[](const SubtargetInfoKV &LHS, const SubtargetInfoKV &RHS) {
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return strcmp(LHS.Key, RHS.Key) < 0;
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}) &&
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"Processor machine model table is not sorted");
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// Find entry
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auto Found =
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std::lower_bound(SchedModels.begin(), SchedModels.end(), CPU);
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if (Found == SchedModels.end() || StringRef(Found->Key) != CPU) {
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if (CPU != "help") // Don't error if the user asked for help.
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errs() << "'" << CPU
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<< "' is not a recognized processor for this target"
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<< " (ignoring processor)\n";
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return MCSchedModel::GetDefaultSchedModel();
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}
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assert(Found->Value && "Missing processor SchedModel value");
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return *(const MCSchedModel *)Found->Value;
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}
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InstrItineraryData
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MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
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const MCSchedModel &SchedModel = getSchedModelForCPU(CPU);
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return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
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}
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void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
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InstrItins = InstrItineraryData(getSchedModel(), Stages, OperandCycles,
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ForwardingPaths);
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}
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