mirror of
https://github.com/RPCS3/llvm-mirror.git
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d61d0211ba
* BPA and BPN do not take a %cc register as a parameter
* SLL/SRL/SRA{r,i}5 are there for a reason - they are ONLY 32-bit instructions
* Likewise, SLL/SRL/SRAX{r,i}6 are only 64-bit
* Added WRCCR{r,i} opcodes
llvm-svn: 6655
210 lines
6.2 KiB
C++
210 lines
6.2 KiB
C++
//===-- llvm/CodeGen/SparcInstrSelectionSupport.h ---------------*- C++ -*-===//
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//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARC_INSTR_SELECTION_SUPPORT_h
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#define SPARC_INSTR_SELECTION_SUPPORT_h
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#include "llvm/DerivedTypes.h"
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#include "SparcInternals.h"
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inline MachineOpCode
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ChooseLoadInstruction(const Type *DestTy)
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{
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switch (DestTy->getPrimitiveID()) {
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case Type::BoolTyID:
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case Type::UByteTyID: return V9::LDUBr;
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case Type::SByteTyID: return V9::LDSBr;
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case Type::UShortTyID: return V9::LDUHr;
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case Type::ShortTyID: return V9::LDSHr;
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case Type::UIntTyID: return V9::LDUWr;
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case Type::IntTyID: return V9::LDSWr;
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case Type::PointerTyID:
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case Type::ULongTyID:
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case Type::LongTyID: return V9::LDXr;
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case Type::FloatTyID: return V9::LDFr;
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case Type::DoubleTyID: return V9::LDDFr;
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default: assert(0 && "Invalid type for Load instruction");
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}
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return 0;
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}
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inline MachineOpCode
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ChooseStoreInstruction(const Type *DestTy)
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{
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switch (DestTy->getPrimitiveID()) {
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case Type::BoolTyID:
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case Type::UByteTyID:
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case Type::SByteTyID: return V9::STBr;
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case Type::UShortTyID:
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case Type::ShortTyID: return V9::STHr;
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case Type::UIntTyID:
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case Type::IntTyID: return V9::STWr;
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case Type::PointerTyID:
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case Type::ULongTyID:
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case Type::LongTyID: return V9::STXr;
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case Type::FloatTyID: return V9::STFr;
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case Type::DoubleTyID: return V9::STDFr;
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default: assert(0 && "Invalid type for Store instruction");
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}
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return 0;
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}
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inline MachineOpCode
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ChooseAddInstructionByType(const Type* resultType)
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{
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MachineOpCode opCode = V9::INVALID_OPCODE;
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if (resultType->isIntegral() ||
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isa<PointerType>(resultType) ||
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isa<FunctionType>(resultType) ||
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resultType == Type::LabelTy)
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{
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opCode = V9::ADDr;
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}
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else
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switch(resultType->getPrimitiveID())
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{
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case Type::FloatTyID: opCode = V9::FADDS; break;
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case Type::DoubleTyID: opCode = V9::FADDD; break;
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default: assert(0 && "Invalid type for ADD instruction"); break;
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}
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return opCode;
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}
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static unsigned
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convertOpcodeFromRegToImm(unsigned Opcode) {
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switch (Opcode) {
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/* arithmetic */
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case V9::ADDr: return V9::ADDi;
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case V9::ADDccr: return V9::ADDcci;
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case V9::ADDCr: return V9::ADDCi;
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case V9::ADDCccr: return V9::ADDCcci;
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case V9::SUBr: return V9::SUBi;
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case V9::SUBccr: return V9::SUBcci;
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case V9::SUBCr: return V9::SUBCi;
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case V9::SUBCccr: return V9::SUBCcci;
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case V9::MULXr: return V9::MULXi;
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case V9::SDIVXr: return V9::SDIVXi;
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case V9::UDIVXr: return V9::UDIVXi;
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/* logical */
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case V9::ANDr: return V9::ANDi;
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case V9::ANDccr: return V9::ANDcci;
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case V9::ANDNr: return V9::ANDNi;
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case V9::ANDNccr: return V9::ANDNcci;
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case V9::ORr: return V9::ORi;
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case V9::ORccr: return V9::ORcci;
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case V9::ORNr: return V9::ORNi;
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case V9::ORNccr: return V9::ORNcci;
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case V9::XORr: return V9::XORi;
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case V9::XORccr: return V9::XORcci;
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case V9::XNORr: return V9::XNORi;
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case V9::XNORccr: return V9::XNORcci;
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/* shift */
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case V9::SLLr5: return V9::SLLi5;
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case V9::SRLr5: return V9::SRLi5;
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case V9::SRAr5: return V9::SRAi5;
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case V9::SLLXr6: return V9::SLLXi6;
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case V9::SRLXr6: return V9::SRLXi6;
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case V9::SRAXr6: return V9::SRAXi6;
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/* Conditional move on int comparison with zero */
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case V9::MOVRZr: return V9::MOVRZi;
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case V9::MOVRLEZr: return V9::MOVRLEZi;
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case V9::MOVRLZr: return V9::MOVRLZi;
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case V9::MOVRNZr: return V9::MOVRNZi;
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case V9::MOVRGZr: return V9::MOVRGZi;
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case V9::MOVRGEZr: return V9::MOVRGEZi;
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/* Conditional move on int condition code */
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case V9::MOVAr: return V9::MOVAi;
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case V9::MOVNr: return V9::MOVNi;
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case V9::MOVNEr: return V9::MOVNEi;
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case V9::MOVEr: return V9::MOVEi;
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case V9::MOVGr: return V9::MOVGi;
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case V9::MOVLEr: return V9::MOVLEi;
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case V9::MOVGEr: return V9::MOVGEi;
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case V9::MOVLr: return V9::MOVLi;
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case V9::MOVGUr: return V9::MOVGUi;
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case V9::MOVLEUr: return V9::MOVLEUi;
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case V9::MOVCCr: return V9::MOVCCi;
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case V9::MOVCSr: return V9::MOVCSi;
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case V9::MOVPOSr: return V9::MOVPOSi;
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case V9::MOVNEGr: return V9::MOVNEGi;
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case V9::MOVVCr: return V9::MOVVCi;
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case V9::MOVVSr: return V9::MOVVSi;
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/* Conditional move of int reg on fp condition code */
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case V9::MOVFAr: return V9::MOVFAi;
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case V9::MOVFNr: return V9::MOVFNi;
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case V9::MOVFUr: return V9::MOVFUi;
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case V9::MOVFGr: return V9::MOVFGi;
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case V9::MOVFUGr: return V9::MOVFUGi;
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case V9::MOVFLr: return V9::MOVFLi;
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case V9::MOVFULr: return V9::MOVFULi;
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case V9::MOVFLGr: return V9::MOVFLGi;
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case V9::MOVFNEr: return V9::MOVFNEi;
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case V9::MOVFEr: return V9::MOVFEi;
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case V9::MOVFUEr: return V9::MOVFUEi;
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case V9::MOVFGEr: return V9::MOVFGEi;
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case V9::MOVFUGEr: return V9::MOVFUGEi;
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case V9::MOVFLEr: return V9::MOVFLEi;
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case V9::MOVFULEr: return V9::MOVFULEi;
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case V9::MOVFOr: return V9::MOVFOi;
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/* load */
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case V9::LDSBr: return V9::LDSBi;
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case V9::LDSHr: return V9::LDSHi;
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case V9::LDSWr: return V9::LDSWi;
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case V9::LDUBr: return V9::LDUBi;
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case V9::LDUHr: return V9::LDUHi;
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case V9::LDUWr: return V9::LDUWi;
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case V9::LDXr: return V9::LDXi;
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case V9::LDFr: return V9::LDFi;
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case V9::LDDFr: return V9::LDDFi;
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case V9::LDQFr: return V9::LDQFi;
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case V9::LDFSRr: return V9::LDFSRi;
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case V9::LDXFSRr: return V9::LDXFSRi;
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/* store */
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case V9::STBr: return V9::STBi;
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case V9::STHr: return V9::STHi;
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case V9::STWr: return V9::STWi;
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case V9::STXr: return V9::STXi;
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case V9::STFr: return V9::STFi;
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case V9::STDFr: return V9::STDFi;
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case V9::STFSRr: return V9::STFSRi;
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case V9::STXFSRr: return V9::STXFSRi;
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/* jump & return */
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case V9::JMPLCALLr: return V9::JMPLCALLi;
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case V9::JMPLRETr: return V9::JMPLRETi;
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case V9::RETURNr: return V9::RETURNi;
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/* save and restore */
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case V9::SAVEr: return V9::SAVEi;
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case V9::RESTOREr: return V9::RESTOREi;
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default:
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// It's already in correct format
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// Or, it's just not handled yet, but an assert() would break LLC
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#if 0
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std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
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<< "\n";
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#endif
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return Opcode;
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}
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}
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#endif
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