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011ef76da2
The previous rev (r310208) failed to account for overflow when subtracting the constants to see if they're suitable for shift/lea. This version add a check for that and more test were added in r310490. We can convert any select-of-constants to math ops: http://rise4fun.com/Alive/d7d For this patch, I'm enhancing an existing x86 transform that uses fake multiplies (they always become shl/lea) to avoid cmov or branching. The current code misses cases where we have a negative constant and a positive constant, so this is just trying to plug that hole. The DAGCombiner diff prevents us from hitting a terrible inefficiency: we can start with a select in IR, create a select DAG node, convert it into a sext, convert it back into a select, and then lower it to sext machine code. Some notes about the test diffs: 1. 2010-08-04-MaskedSignedCompare.ll - We were creating control flow that didn't exist in the IR. 2. memcmp.ll - Choose -1 or 1 is the case that got me looking at this again. We could avoid the push/pop in some cases if we used 'movzbl %al' instead of an xor on a different reg? That's a post-DAG problem though. 3. mul-constant-result.ll - The trade-off between sbb+not vs. setne+neg could be addressed if that's a regression, but those would always be nearly equivalent. 4. pr22338.ll and sext-i1.ll - These tests have undef operands, so we don't actually care about these diffs. 5. sbb.ll - This shows a win for what is likely a common case: choose -1 or 0. 6. select.ll - There's another borderline case here: cmp+sbb+or vs. test+set+lea? Also, sbb+not vs. setae+neg shows up again. 7. select_const.ll - These are motivating cases for the enhancement; replace cmov with cheaper ops. Assembly differences between movzbl and xor to avoid a partial reg stall are caused later by the X86 Fixup SetCC pass. Differential Revision: https://reviews.llvm.org/D35340 llvm-svn: 310717
177 lines
4.2 KiB
LLVM
177 lines
4.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -disable-cgp-branch-opts | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; rdar://7573216
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; PR6146
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define i32 @t1(i32 %x) nounwind readnone ssp {
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; X32-LABEL: t1:
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; X32: # BB#0:
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; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t1:
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; X64: # BB#0:
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; X64-NEXT: cmpl $1, %edi
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; X64-NEXT: sbbl %eax, %eax
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; X64-NEXT: retq
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%t0 = icmp eq i32 %x, 0
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%if = select i1 %t0, i32 -1, i32 0
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ret i32 %if
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}
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define i32 @t2(i32 %x) nounwind readnone ssp {
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; X32-LABEL: t2:
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; X32: # BB#0:
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; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t2:
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; X64: # BB#0:
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; X64-NEXT: cmpl $1, %edi
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; X64-NEXT: sbbl %eax, %eax
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; X64-NEXT: retq
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%t0 = icmp eq i32 %x, 0
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%if = sext i1 %t0 to i32
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ret i32 %if
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}
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define i32 @t3() nounwind readonly {
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; X32-LABEL: t3:
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; X32: # BB#0: # %entry
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; X32-NEXT: cmpl $1, %eax
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: cmpl %eax, %eax
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t3:
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; X64: # BB#0: # %entry
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: testl %eax, %eax
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; X64-NEXT: sete %al
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; X64-NEXT: negq %rax
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; X64-NEXT: cmpq %rax, %rax
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: retq
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entry:
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%not.tobool = icmp eq i32 undef, 0
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%cond = sext i1 %not.tobool to i32
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%conv = sext i1 %not.tobool to i64
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%add13 = add i64 0, %conv
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%cmp = icmp ult i64 undef, %add13
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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br label %if.end
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if.end:
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%xor27 = xor i32 undef, %cond
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ret i32 0
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}
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define i32 @t4(i64 %x) nounwind readnone ssp {
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; X32-LABEL: t4:
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; X32: # BB#0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: sete %al
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; X32-NEXT: negl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: t4:
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; X64: # BB#0:
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; X64-NEXT: cmpq $1, %rdi
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; X64-NEXT: sbbl %eax, %eax
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; X64-NEXT: retq
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%t0 = icmp eq i64 %x, 0
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%t1 = sext i1 %t0 to i32
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ret i32 %t1
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}
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define i64 @t5(i32 %x) nounwind readnone ssp {
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; X32-LABEL: t5:
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; X32: # BB#0:
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; X32-NEXT: cmpl $1, {{[0-9]+}}(%esp)
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; X32-NEXT: sbbl %eax, %eax
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; X32-NEXT: movl %eax, %edx
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; X32-NEXT: retl
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;
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; X64-LABEL: t5:
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; X64: # BB#0:
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; X64-NEXT: cmpl $1, %edi
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; X64-NEXT: sbbq %rax, %rax
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; X64-NEXT: retq
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%t0 = icmp eq i32 %x, 0
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%t1 = sext i1 %t0 to i64
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ret i64 %t1
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}
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; sext (xor Bool, -1) --> sub (zext Bool), 1
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define i32 @select_0_or_1s(i1 %cond) {
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; X32-LABEL: select_0_or_1s:
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; X32: # BB#0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: decl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: select_0_or_1s:
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; X64: # BB#0:
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; X64-NEXT: # kill: %EDI<def> %EDI<kill> %RDI<def>
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; X64-NEXT: andl $1, %edi
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; X64-NEXT: leal -1(%rdi), %eax
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; X64-NEXT: retq
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%not = xor i1 %cond, 1
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%sext = sext i1 %not to i32
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ret i32 %sext
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}
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; sext (xor Bool, -1) --> sub (zext Bool), 1
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define i32 @select_0_or_1s_zeroext(i1 zeroext %cond) {
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; X32-LABEL: select_0_or_1s_zeroext:
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; X32: # BB#0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: decl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: select_0_or_1s_zeroext:
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; X64: # BB#0:
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: decl %eax
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; X64-NEXT: retq
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%not = xor i1 %cond, 1
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%sext = sext i1 %not to i32
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ret i32 %sext
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}
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; sext (xor Bool, -1) --> sub (zext Bool), 1
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define i32 @select_0_or_1s_signext(i1 signext %cond) {
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; X32-LABEL: select_0_or_1s_signext:
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; X32: # BB#0:
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; X32-NEXT: movb {{[0-9]+}}(%esp), %al
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; X32-NEXT: andb $1, %al
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; X32-NEXT: movzbl %al, %eax
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; X32-NEXT: decl %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: select_0_or_1s_signext:
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; X64: # BB#0:
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; X64-NEXT: andb $1, %dil
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: decl %eax
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; X64-NEXT: retq
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%not = xor i1 %cond, 1
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%sext = sext i1 %not to i32
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ret i32 %sext
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}
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