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891074f69a
The X-form TLS load/store instructions added for optimizing the initial-exec sequence in https://reviews.llvm.org/rL327635 fail to assemble. llvm-mc fails with the error: invalid operand for instruction. This patch adds these instructions into a block with isAsmParserOnly, similar to how ADD8TLS_ is currently handled. Differential Revision: https://reviews.llvm.org/D47382 llvm-svn: 333374
42 lines
1.4 KiB
ArmAsm
42 lines
1.4 KiB
ArmAsm
# RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj %s | \
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# RUN: llvm-readobj -r | FileCheck %s
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.text
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addis 3, 13, t@tprel@ha
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addi 3, 3, t@tprel@l
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addis 3, 2, t@got@tprel@ha
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ld 3, t@got@tprel@l(3)
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lwzx 4, 3, t@tls
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lhzx 4, 3, t@tls
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lbzx 4, 3, t@tls
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ldx 4, 3, t@tls
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stbx 4, 3, t@tls
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sthx 4, 3, t@tls
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stwx 4, 3, t@tls
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stdx 4, 3, t@tls
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.type t,@object
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.section .tbss,"awT",@nobits
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.globl t
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.align 2
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t:
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.long 0
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.size t, 4
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# Check for a pair of R_PPC64_TPREL16_HA / R_PPC64_TPREL16_LO relocs
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# against the thread-local symbol 't'.
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# CHECK: Relocations [
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# CHECK: Section ({{[0-9]+}}) .rela.text {
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_HA t
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TPREL16_LO t
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_HA t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_GOT_TPREL16_LO_DS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: 0x{{[0-9,A-F]+}} R_PPC64_TLS t 0x0
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# CHECK-NEXT: }
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