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Fork of llvm with experimental commits and workarounds for RPCS3
d89900e14c
This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. llvm-svn: 133105 |
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autoconf | ||
bindings | ||
cmake | ||
docs | ||
examples | ||
include | ||
lib | ||
projects | ||
runtime | ||
test | ||
tools | ||
unittests | ||
utils | ||
website | ||
.gitignore | ||
build-for-llvm-top.sh | ||
CMakeLists.txt | ||
configure | ||
CREDITS.TXT | ||
LICENSE.TXT | ||
llvm.spec.in | ||
Makefile | ||
Makefile.common | ||
Makefile.config.in | ||
Makefile.rules | ||
ModuleInfo.txt | ||
README.txt |
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