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117 lines
3.8 KiB
TableGen
117 lines
3.8 KiB
TableGen
//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the SparcV8 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstV8 : Instruction { // SparcV8 instruction baseline
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field bits<32> Inst;
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let Namespace = "V8";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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// Bit attributes specific to SparcV8 instructions
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bit isPasi = 0; // Does this instruction affect an alternate addr space?
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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include "SparcV8InstrInfo_F2.td"
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include "SparcV8InstrInfo_F3.td"
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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def PHI : InstV8 {
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let Name = "PHI";
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}
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def ADJCALLSTACKDOWN : InstV8 {
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let Name = "ADJCALLSTACKDOWN";
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}
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def ADJCALLSTACKUP : InstV8 {
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let Name = "ADJCALLSTACKUP";
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}
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// Section A.3 - Synthetic Instructions, p. 85
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let isReturn = 1, isTerminator = 1, simm13 = 8 in
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def RET : F3_2<2, 0b111000, "ret">;
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let isReturn = 1, isTerminator = 1, simm13 = 8 in
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def RETL: F3_2<2, 0b111000, "retl">;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSBmr: F3_2<3, 0b001001, "ldsb">;
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def LDSHmr: F3_2<3, 0b001010, "ldsh">;
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def LDUBmr: F3_2<3, 0b000001, "ldub">;
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def LDUHmr: F3_2<3, 0b000010, "lduh">;
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def LDmr : F3_2<3, 0b000000, "ld">;
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def LDDmr : F3_2<3, 0b000011, "ldd">;
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// Section B.4 - Store Integer Instructions, p. 95
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def STBrm : F3_2<3, 0b000101, "stb">;
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def STHrm : F3_2<3, 0b000110, "sth">;
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def STrm : F3_2<3, 0b000100, "st">;
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def STDrm : F3_2<3, 0b000111, "std">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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// Section B.10 - NOP Instruction, p. 105
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// (It's a special case of SETHI)
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let rd = 0, imm = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDri : F3_2<2, 0b000001, "and">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLri : F3_1<2, 0b100101, "sll">;
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def SRLri : F3_1<2, 0b100110, "srl">;
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def SRAri : F3_1<2, 0b100111, "sra">;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000, "add">;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100, "sub">;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010, "umul">;
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def SMULrr : F3_1<2, 0b001011, "smul">;
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// Section B.20 - SAVE and RESTORE, p. 117
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def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
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def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
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def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
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def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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def CALL : InstV8 {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let Name = "call";
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let isCall = 1;
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}
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// Section B.25 - Jump and Link, p. 126
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def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
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