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e325c693a5
FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. llvm-svn: 101754
58 lines
3.0 KiB
TableGen
58 lines
3.0 KiB
TableGen
//===- SPUSchedule.td - Cell Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Even pipeline:
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def EVEN_UNIT : FuncUnit; // Even execution unit: (PC & 0x7 == 000)
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def ODD_UNIT : FuncUnit; // Odd execution unit: (PC & 0x7 == 100)
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for Cell SPU
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//===----------------------------------------------------------------------===//
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def LoadStore : InstrItinClass; // ODD_UNIT
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def BranchHints : InstrItinClass; // ODD_UNIT
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def BranchResolv : InstrItinClass; // ODD_UNIT
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def ChanOpSPR : InstrItinClass; // ODD_UNIT
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def ShuffleOp : InstrItinClass; // ODD_UNIT
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def SelectOp : InstrItinClass; // ODD_UNIT
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def GatherOp : InstrItinClass; // ODD_UNIT
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def LoadNOP : InstrItinClass; // ODD_UNIT
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def ExecNOP : InstrItinClass; // EVEN_UNIT
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def SPrecFP : InstrItinClass; // EVEN_UNIT
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def DPrecFP : InstrItinClass; // EVEN_UNIT
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def FPInt : InstrItinClass; // EVEN_UNIT (FP<->integer)
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def ByteOp : InstrItinClass; // EVEN_UNIT
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def IntegerOp : InstrItinClass; // EVEN_UNIT
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def IntegerMulDiv: InstrItinClass; // EVEN_UNIT
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def RotateShift : InstrItinClass; // EVEN_UNIT
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def ImmLoad : InstrItinClass; // EVEN_UNIT
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/* Note: The itinerary for the Cell SPU is somewhat contrived... */
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def SPUItineraries : ProcessorItineraries<[ODD_UNIT, EVEN_UNIT], [
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InstrItinData<LoadStore , [InstrStage<6, [ODD_UNIT]>]>,
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InstrItinData<BranchHints , [InstrStage<6, [ODD_UNIT]>]>,
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InstrItinData<BranchResolv, [InstrStage<4, [ODD_UNIT]>]>,
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InstrItinData<ChanOpSPR , [InstrStage<6, [ODD_UNIT]>]>,
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InstrItinData<ShuffleOp , [InstrStage<4, [ODD_UNIT]>]>,
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InstrItinData<SelectOp , [InstrStage<4, [ODD_UNIT]>]>,
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InstrItinData<GatherOp , [InstrStage<4, [ODD_UNIT]>]>,
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InstrItinData<LoadNOP , [InstrStage<1, [ODD_UNIT]>]>,
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InstrItinData<ExecNOP , [InstrStage<1, [EVEN_UNIT]>]>,
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InstrItinData<SPrecFP , [InstrStage<6, [EVEN_UNIT]>]>,
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InstrItinData<DPrecFP , [InstrStage<13, [EVEN_UNIT]>]>,
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InstrItinData<FPInt , [InstrStage<2, [EVEN_UNIT]>]>,
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InstrItinData<ByteOp , [InstrStage<4, [EVEN_UNIT]>]>,
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InstrItinData<IntegerOp , [InstrStage<2, [EVEN_UNIT]>]>,
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InstrItinData<RotateShift , [InstrStage<4, [EVEN_UNIT]>]>,
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InstrItinData<IntegerMulDiv,[InstrStage<7, [EVEN_UNIT]>]>,
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InstrItinData<ImmLoad , [InstrStage<2, [EVEN_UNIT]>]>
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]>;
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