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Target implementations of getRegAllocationHints() should use the provided allocation order, and they can never return hints outside the order. This is already documented in TargetRegisterInfo.h. <rdar://problem/13240556> llvm-svn: 175540
53 lines
1.8 KiB
C++
53 lines
1.8 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements an allocation order for virtual registers.
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//
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// The preferred allocation order for a virtual register depends on allocation
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// hints and target hooks. The AllocationOrder class encapsulates all of that.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "regalloc"
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#include "AllocationOrder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Compare VirtRegMap::getRegAllocPref().
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AllocationOrder::AllocationOrder(unsigned VirtReg,
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const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo)
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: Pos(0) {
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const MachineFunction &MF = VRM.getMachineFunction();
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const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
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Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM);
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rewind();
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DEBUG({
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if (!Hints.empty()) {
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dbgs() << "hints:";
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for (unsigned I = 0, E = Hints.size(); I != E; ++I)
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dbgs() << ' ' << PrintReg(Hints[I], TRI);
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dbgs() << '\n';
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}
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});
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#ifndef NDEBUG
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for (unsigned I = 0, E = Hints.size(); I != E; ++I)
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assert(std::find(Order.begin(), Order.end(), Hints[I]) != Order.end() &&
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"Target hint is outside allocation order.");
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#endif
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}
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