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9099fd3422
In addition to the original commit, tighten the condition for when to pad empty functions to COFF Windows. This avoids running into problems when targeting e.g. Win32 AMDGPU, which caused test failures when this was committed initially. llvm-svn: 301047
75 lines
2.9 KiB
C++
75 lines
2.9 KiB
C++
//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
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#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
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#include "ARMBaseInstrInfo.h"
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#include "ThumbRegisterInfo.h"
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namespace llvm {
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class ARMSubtarget;
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class ScheduleHazardRecognizer;
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class Thumb2InstrInfo : public ARMBaseInstrInfo {
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ThumbRegisterInfo RI;
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public:
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explicit Thumb2InstrInfo(const ARMSubtarget &STI);
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/// Return the noop instruction to use for a noop.
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void getNoop(MCInst &NopInst) const override;
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const override;
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void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
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MachineBasicBlock *NewDest) const override;
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bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) const override;
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void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
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private:
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void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
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};
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/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
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/// to llvm::getInstrPredicate except it returns AL for conditional branch
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/// instructions which are "predicated", but are not in IT blocks.
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ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
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}
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#endif
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