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10180bb2a1
This header already includes a CodeGen header and is implemented in lib/CodeGen, so move the header there to match. This fixes a link error with modular codegeneration builds - where a header and its implementation are circularly dependent and so need to be in the same library, not split between two like this. llvm-svn: 317379
150 lines
6.4 KiB
C++
150 lines
6.4 KiB
C++
//===-- PPCFrameLowering.h - Define frame lowering for PowerPC --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
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#define LLVM_LIB_TARGET_POWERPC_PPCFRAMELOWERING_H
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#include "PPC.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class PPCSubtarget;
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class PPCFrameLowering: public TargetFrameLowering {
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const PPCSubtarget &Subtarget;
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const unsigned ReturnSaveOffset;
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const unsigned TOCSaveOffset;
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const unsigned FramePointerSaveOffset;
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const unsigned LinkageSize;
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const unsigned BasePointerSaveOffset;
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/**
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* \brief Find register[s] that can be used in function prologue and epilogue
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*
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* Find register[s] that can be use as scratch register[s] in function
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* prologue and epilogue to save various registers (Link Register, Base
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* Pointer, etc.). Prefer R0/R12, if available. Otherwise choose whatever
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* register[s] are available.
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*
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* This method will return true if it is able to find enough unique scratch
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* registers (1 or 2 depending on the requirement). If it is unable to find
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* enough available registers in the block, it will return false and set
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* any passed output parameter that corresponds to a required unique register
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* to PPC::NoRegister.
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*
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* \param[in] MBB The machine basic block to find an available register for
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* \param[in] UseAtEnd Specify whether the scratch register will be used at
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* the end of the basic block (i.e., will the scratch
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* register kill a register defined in the basic block)
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* \param[in] TwoUniqueRegsRequired Specify whether this basic block will
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* require two unique scratch registers.
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* \param[out] SR1 The scratch register to use
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* \param[out] SR2 The second scratch register. If this pointer is not null
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* the function will attempt to set it to an available
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* register regardless of whether there is a hard requirement
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* for two unique scratch registers.
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* \return true if the required number of registers was found.
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* false if the required number of scratch register weren't available.
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* If either output parameter refers to a required scratch register
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* that isn't available, it will be set to an invalid value.
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*/
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bool findScratchRegister(MachineBasicBlock *MBB,
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bool UseAtEnd,
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bool TwoUniqueRegsRequired = false,
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unsigned *SR1 = nullptr,
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unsigned *SR2 = nullptr) const;
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bool twoUniqueScratchRegsRequired(MachineBasicBlock *MBB) const;
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/**
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* \brief Create branch instruction for PPC::TCRETURN* (tail call return)
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*
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* \param[in] MBB that is terminated by PPC::TCRETURN*
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*/
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void createTailCallBranchInstr(MachineBasicBlock &MBB) const;
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public:
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PPCFrameLowering(const PPCSubtarget &STI);
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unsigned determineFrameLayout(MachineFunction &MF,
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bool UpdateMF = true,
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bool UseEstimate = false) const;
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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bool hasFP(const MachineFunction &MF) const override;
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bool needsFP(const MachineFunction &MF) const;
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void replaceFPWithRealFP(MachineFunction &MF) const;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS = nullptr) const override;
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void processFunctionBeforeFrameFinalized(MachineFunction &MF,
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RegScavenger *RS = nullptr) const override;
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void addScavengingSpillSlot(MachineFunction &MF, RegScavenger *RS) const;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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const std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const override;
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bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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std::vector<CalleeSavedInfo> &CSI,
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const TargetRegisterInfo *TRI) const override;
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/// targetHandlesStackFrameRounding - Returns true if the target is
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/// responsible for rounding up the stack frame (probably at emitPrologue
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/// time).
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bool targetHandlesStackFrameRounding() const override { return true; }
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/// getReturnSaveOffset - Return the previous frame offset to save the
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/// return address.
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unsigned getReturnSaveOffset() const { return ReturnSaveOffset; }
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/// getTOCSaveOffset - Return the previous frame offset to save the
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/// TOC register -- 64-bit SVR4 ABI only.
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unsigned getTOCSaveOffset() const { return TOCSaveOffset; }
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/// getFramePointerSaveOffset - Return the previous frame offset to save the
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/// frame pointer.
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unsigned getFramePointerSaveOffset() const { return FramePointerSaveOffset; }
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/// getBasePointerSaveOffset - Return the previous frame offset to save the
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/// base pointer.
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unsigned getBasePointerSaveOffset() const { return BasePointerSaveOffset; }
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/// getLinkageSize - Return the size of the PowerPC ABI linkage area.
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///
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unsigned getLinkageSize() const { return LinkageSize; }
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const SpillSlot *
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getCalleeSavedSpillSlots(unsigned &NumEntries) const override;
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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/// Methods used by shrink wrapping to determine if MBB can be used for the
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/// function prologue/epilogue.
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bool canUseAsPrologue(const MachineBasicBlock &MBB) const override;
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bool canUseAsEpilogue(const MachineBasicBlock &MBB) const override;
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};
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} // End llvm namespace
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#endif
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