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767e9d16e6
Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. llvm-svn: 136845
19 lines
829 B
ArmAsm
19 lines
829 B
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
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@ CHECK: ldrsbt r1, [r0], r2 @ encoding: [0xd2,0x10,0xb0,0xe0]
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@ CHECK: ldrsbt r1, [r0], #4 @ encoding: [0xd4,0x10,0xf0,0xe0]
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@ CHECK: ldrsht r1, [r0], r2 @ encoding: [0xf2,0x10,0xb0,0xe0]
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@ CHECK: ldrsht r1, [r0], #4 @ encoding: [0xf4,0x10,0xf0,0xe0]
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@ CHECK: ldrht r1, [r0], r2 @ encoding: [0xb2,0x10,0xb0,0xe0]
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@ CHECK: ldrht r1, [r0], #4 @ encoding: [0xb4,0x10,0xf0,0xe0]
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@ CHECK: strht r1, [r0], r2 @ encoding: [0xb2,0x10,0xa0,0xe0]
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@ CHECK: strht r1, [r0], #4 @ encoding: [0xb4,0x10,0xe0,0xe0]
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ldrsbt r1, [r0], r2
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ldrsbt r1, [r0], #4
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ldrsht r1, [r0], r2
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ldrsht r1, [r0], #4
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ldrht r1, [r0], r2
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ldrht r1, [r0], #4
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strht r1, [r0], r2
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strht r1, [r0], #4
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