mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-19 11:41:53 +00:00
c1696e995e
Adds vcc to output string input for e32. Allows option of using e64 encoding with assembler. Also fixes these instructions not implicitly reading exec. llvm-svn: 247074
63 lines
1.9 KiB
ArmAsm
63 lines
1.9 KiB
ArmAsm
// RUN: not llvm-mc -arch=amdgcn %s 2>&1 | FileCheck %s
|
|
// RUN: not llvm-mc -arch=amdgcn -mcpu=SI %s 2>&1 | FileCheck %s
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Generic checks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
v_mul_i32_i24 v1, v2, 100
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// _e32 checks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Immediate src1
|
|
v_mul_i32_i24_e32 v1, v2, 100
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
// sgpr src1
|
|
v_mul_i32_i24_e32 v1, v2, s3
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// _e64 checks
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Immediate src0
|
|
v_mul_i32_i24_e64 v1, 100, v3
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
// Immediate src1
|
|
v_mul_i32_i24_e64 v1, v2, 100
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_add_i32_e32 v1, s[0:1], v2, v3
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, s[2:3]
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3]
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, -1
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, 123
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, vcc, v2, v3, s0
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e32 v1, -1, v2, v3, s0
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32_e64 v1, s[0:1], v2, v3, 123
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
v_addc_u32 v1, s[0:1], v2, v3, 123
|
|
// CHECK: error: invalid operand for instruction
|
|
|
|
// TODO: Constant bus restrictions
|