Alex Bradbury e4dd444e6f [RISCV] MC layer support for the standard RV32D instruction set extension ...

As the FPR32 and FPR64 registers have the same names, use 
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an 
FPR64 when necessary. The rest of this patch is very similar to the RV32F 
patch.

Differential Revision: https://reviews.llvm.org/D39895

llvm-svn: 320023

2017-12-07 10:46:23 +00:00

..

elf-header.s

[RISCV] Bugfix createRISCVELFObjectWriter

2017-10-18 16:11:31 +00:00

fixups-diagnostics.s

[RISCV] Add common fixups and relocations

2017-09-28 08:26:24 +00:00

fixups.s

[RISCV] Add common fixups and relocations

2017-09-28 08:26:24 +00:00

hilo-constaddr.s

[RISCV] Add common fixups and relocations

2017-09-28 08:26:24 +00:00

lit.local.cfg

…

relocations.s

[RISCV] Add common fixups and relocations

2017-09-28 08:26:24 +00:00

rv32a-invalid.s

[RISCV] MC layer support for the standard RV32A instruction set extension

2017-11-09 15:00:03 +00:00

rv32a-valid.s

[RISCV] MC layer support for the standard RV32A instruction set extension

2017-11-09 15:00:03 +00:00

rv32d-invalid.s

[RISCV] MC layer support for the standard RV32D instruction set extension

2017-12-07 10:46:23 +00:00

rv32d-valid.s

[RISCV] MC layer support for the standard RV32D instruction set extension

2017-12-07 10:46:23 +00:00

rv32f-invalid.s

[RISCV] MC layer support for the standard RV32D instruction set extension

2017-12-07 10:46:23 +00:00

rv32f-valid.s

[RISCV] MC layer support for the standard RV32F instruction set extension

2017-12-07 10:26:05 +00:00

rv32i-invalid.s

[RISCV] MC layer support for the standard RV32F instruction set extension

2017-12-07 10:26:05 +00:00

rv32i-valid.s

[RISCV] Add common fixups and relocations

2017-09-28 08:26:24 +00:00

rv32m-valid.s

[RISCV] MC layer support for the standard RV32M instruction set extension

2017-11-09 14:46:30 +00:00