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591bfa1e0b
This feature is needed in order to support shifts of more than 255 bits on large integer types. This changes the syntax for llvm assembly to make shl, ashr and lshr instructions look like a binary operator: shl i32 %X, 1 instead of shl i32 %X, i8 1 Additionally, this should help a few passes perform additional optimizations. llvm-svn: 33776
27 lines
785 B
LLVM
27 lines
785 B
LLVM
; RUN: llvm-as < %s | llc -march=arm &&
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; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 &&
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; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep "uxtb" | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep "uxtab" | wc -l | grep 1 &&
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; RUN: llvm-as < %s | llc -march=arm -mattr=+v6 | grep "uxth" | wc -l | grep 1
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define i8 @test1(i32 %A.u) zext {
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%B.u = trunc i32 %A.u to i8
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ret i8 %B.u
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}
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define i32 @test2(i32 %A.u, i32 %B.u) zext {
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%C.u = trunc i32 %B.u to i8
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%D.u = zext i8 %C.u to i32
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%E.u = add i32 %A.u, %D.u
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ret i32 %E.u
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}
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define i32 @test3(i32 %A.u) zext {
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%B.u = lshr i32 %A.u, 8
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%C.u = shl i32 %A.u, 24
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%D.u = or i32 %B.u, %C.u
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%E.u = trunc i32 %D.u to i16
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%F.u = zext i16 %E.u to i32
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ret i32 %F.u
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}
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