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019ae7d515
That's only a required extension as of v8.1a. Remove it from the "generic" CPU as well: it should only support the base ISA (and binutils agrees). Also unify the MC tests into crc.s and arm64-crc32.s llvm-svn: 302077
58 lines
1.2 KiB
ArmAsm
58 lines
1.2 KiB
ArmAsm
// RUN: not llvm-mc -triple aarch64-unknown-none-eabi -filetype asm -o - %s 2>&1 | FileCheck %s
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.arch axp64
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# CHECK: error: unknown arch name
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# CHECK: .arch axp64
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# CHECK: ^
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.arch armv8
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aese v0.8h, v1.8h
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# CHECK: error: invalid operand for instruction
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# CHECK: aese v0.8h, v1.8h
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# CHECK: ^
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// We silently ignore invalid features.
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.arch armv8+foo
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aese v0.8h, v1.8h
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# CHECK: error: invalid operand for instruction
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# CHECK: aese v0.8h, v1.8h
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# CHECK: ^
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.arch armv8+crypto
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.arch armv8
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aese v0.8h, v1.8h
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# CHECK: error: invalid operand for instruction
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# CHECK: aese v0.8h, v1.8h
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# CHECK: ^
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.arch armv8.1-a+noras
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esb
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# CHECK: error: instruction requires: ras
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# CHECK: esb
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// PR32873: without extra features, '.arch' is currently ignored.
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// Add an unrelated feature to accept the directive.
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.arch armv8+crc
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casa w5, w7, [x19]
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# CHECK: error: instruction requires: lse
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# CHECK: casa w5, w7, [x19]
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.arch armv8+crypto
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crc32b w0, w1, w2
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# CHECK: error: instruction requires: crc
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# CHECK: crc32b w0, w1, w2
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.arch armv8.1-a+nolse
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casa w5, w7, [x20]
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# CHECK: error: instruction requires: lse
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# CHECK: casa w5, w7, [x20]
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