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Ekaterina Romanova eda4e2e4a7 SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction. AMD's processors family K7, K8, K10, K12, K15 and K16 are known to have SHLD/SHRD instructions with very poor latency. Optimization guides for these processors recommend using an alternative sequence of instructions. For these AMD's processors, I disabled folding (or (x << c) \| (y >> (64 - c))) when we are not optimizing for size. It might be beneficial to disable this folding for some of the Intel's processors. However, since I couldn't find specific recommendations regarding using SHLD/SHRD instructions on Intel's processors, I haven't disabled this peephole for Intel. llvm-svn: 195383		2013-11-21 23:21:26 +00:00
autoconf
bindings	[OCaml] Unbreak make install by providing ocamldoc target	2013-11-21 10:10:16 +00:00
cmake
docs	Remove dangling documentation. llvm-prof was deleted a while ago.	2013-11-21 19:32:37 +00:00
examples
include	Whitespace.	2013-11-21 11:08:31 +00:00
lib	SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.	2013-11-21 23:21:26 +00:00
projects
test	SHLD/SHRD are VectorPath (microcode) instructions known to have poor latency on certain architectures. While generating SHLD/SHRD instructions is acceptable when optimizing for size, optimizing for speed on these platforms should be implemented using alternative sequences of instructions composed of add, adc, shr, shl, or and lea which are directPath instructions. These alternative instructions not only have a lower latency but they also increase the decode bandwidth by allowing simultaneous decoding of a third directPath instruction.	2013-11-21 23:21:26 +00:00
tools
unittests	[PM] Widen the interface for invalidate on an analysis result now that	2013-11-21 10:53:05 +00:00
utils
.arcconfig
.clang-format
.gitignore
CMakeLists.txt	CMake: Some changes to package version names:	2013-11-21 22:47:21 +00:00
CODE_OWNERS.TXT
configure
CREDITS.TXT
LICENSE.TXT
llvm.spec.in
LLVMBuild.txt
Makefile
Makefile.common
Makefile.config.in
Makefile.rules
README.txt

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