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efffaf5cb4
Summary:
This is just an idea, really two ideas. I expect some push-back,
but I realize that posting a diff is the most comprehensive way to express
these concepts.
This patch introduces a Stage class which represents the
various stages of an instruction pipeline. As a start, I have created a simple
FetchStage that is based on existing logic for how MCA produces
instructions, but now encapsulated in a Stage. The idea should become more concrete
once we introduce additional stages. The idea being, that when a stage completes,
the next stage in the pipeline will be executed. Stages are chained together
as a singly linked list to closely model a real pipeline. For now there is only one stage,
so the stage-to-stage flow of instructions isn't immediately obvious.
Eventually, Stage will also handle event notifications, but that functionality
is not complete, and not destined for this patch. Ideally, an interested party
can register for notifications from a particular stage. Callbacks will be issued to
these listeners at various points in the execution of the stage.
For now, eventing functionality remains similar to what it has been in mca::Backend.
We will be building-up the Stage class as we move on, such as adding debug output.
This patch also removes the unique_ptr<Instruction> return value from
InstrBuilder::createInstruction. An Instruction pointer is still produced,
but now it's up to the caller to decide how that item should be managed post-allocation
(e.g., smart pointer). This allows the Fetch stage to create instructions and
manage the lifetime of those instructions as it wishes, and not have to be bound to any
specific managed pointer type. Other callers of createInstruction might have different
requirements, and thus can manage the pointer to fit their needs. Another idea would be to push the
ownership to the RCU.
Currently, the FetchStage will wrap the Instruction
pointer in a shared_ptr. This allows us to remove the Instruction container in
Backend, which was probably going to disappear, or move, at some point anyways.
Note that I did run these changes through valgrind, to make sure we are not leaking
memory. While the shared_ptr comes with some additional overhead it relieves us
from having to manage a list of generated instructions, and/or make lookup calls
to remove the instructions.
I realize that both the Stage class and the Instruction pointer management
(mentioned directly above) are separate but related ideas, and probably should
land as separate patches; I am happy to do that if either idea is decent.
The main reason these two ideas are together is that
Stage::execute() can mutate an InstRef. For the fetch stage, the InstRef is populated
as the primary action of that stage (execute()). I didn't want to change the Stage interface
to support the idea of generating an instruction. Ideally, instructions are to
be pushed through the pipeline. I didn't want to draw too much of a
specialization just for the fetch stage. Excuse the word-salad.
Reviewers: andreadb, courbet, RKSimon
Reviewed By: andreadb
Subscribers: llvm-commits, mgorny, javed.absar, tschuett, gbedwell
Differential Revision: https://reviews.llvm.org/D46741
llvm-svn: 332390
98 lines
3.6 KiB
C++
98 lines
3.6 KiB
C++
//===--------------------- Backend.h ----------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements an OoO backend for the llvm-mca tool.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_BACKEND_H
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#define LLVM_TOOLS_LLVM_MCA_BACKEND_H
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#include "Dispatch.h"
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#include "FetchStage.h"
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#include "InstrBuilder.h"
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#include "Scheduler.h"
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namespace mca {
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class HWEventListener;
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class HWInstructionEvent;
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class HWStallEvent;
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/// An out of order backend for a specific subtarget.
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///
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/// It emulates an out-of-order execution of instructions. Instructions are
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/// fetched from a MCInst sequence managed by an initial 'Fetch' stage.
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/// Instructions are firstly fetched, then dispatched to the schedulers, and
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/// then executed.
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///
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/// This class tracks the lifetime of an instruction from the moment where
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/// it gets dispatched to the schedulers, to the moment where it finishes
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/// executing and register writes are architecturally committed.
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/// In particular, it monitors changes in the state of every instruction
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/// in flight.
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///
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/// Instructions are executed in a loop of iterations. The number of iterations
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/// is defined by the SourceMgr object, which is managed by the initial stage
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/// of the instruction pipeline.
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///
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/// The Backend entry point is method 'run()' which executes cycles in a loop
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/// until there are new instructions to dispatch, and not every instruction
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/// has been retired.
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///
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/// Internally, the Backend collects statistical information in the form of
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/// histograms. For example, it tracks how the dispatch group size changes
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/// over time.
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class Backend {
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const llvm::MCSubtargetInfo &STI;
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/// This is the initial stage of the pipeline.
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/// TODO: Eventually this will become a list of unique Stage* that this
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/// backend pipeline executes.
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std::unique_ptr<FetchStage> Fetch;
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std::unique_ptr<Scheduler> HWS;
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std::unique_ptr<DispatchUnit> DU;
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std::set<HWEventListener *> Listeners;
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unsigned Cycles;
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void runCycle(unsigned Cycle);
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public:
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Backend(const llvm::MCSubtargetInfo &Subtarget,
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const llvm::MCRegisterInfo &MRI,
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std::unique_ptr<FetchStage> InitialStage, unsigned DispatchWidth = 0,
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unsigned RegisterFileSize = 0, unsigned LoadQueueSize = 0,
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unsigned StoreQueueSize = 0, bool AssumeNoAlias = false)
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: STI(Subtarget), Fetch(std::move(InitialStage)),
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HWS(llvm::make_unique<Scheduler>(this, Subtarget.getSchedModel(),
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LoadQueueSize, StoreQueueSize,
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AssumeNoAlias)),
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DU(llvm::make_unique<DispatchUnit>(this, Subtarget.getSchedModel(), MRI,
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RegisterFileSize, DispatchWidth,
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HWS.get())),
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Cycles(0) {
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HWS->setDispatchUnit(DU.get());
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}
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void run();
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void addEventListener(HWEventListener *Listener);
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void notifyCycleBegin(unsigned Cycle);
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void notifyInstructionEvent(const HWInstructionEvent &Event);
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void notifyStallEvent(const HWStallEvent &Event);
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void notifyResourceAvailable(const ResourceRef &RR);
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void notifyReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
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void notifyReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
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void notifyCycleEnd(unsigned Cycle);
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};
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} // namespace mca
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#endif
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