llvm-mirror/lib/Target/Sparc
Dan Gohman b5ec39e2dc Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.
Note that "hasDotLocAndDotFile"-style debug info was already broken;
people wanting this functionality should implement it in the
AsmPrinter/DwarfWriter code.

llvm-svn: 89711
2009-11-23 23:20:51 +00:00
..
AsmPrinter Move DebugInfo checks into EmitComments and remove them from 2009-11-13 21:34:57 +00:00
TargetInfo
CMakeLists.txt
DelaySlotFiller.cpp
FPMover.cpp
Makefile
README.txt
Sparc.h
Sparc.td
SparcCallingConv.td
SparcInstrFormats.td
SparcInstrInfo.cpp
SparcInstrInfo.h
SparcInstrInfo.td Set isBarrier = 1 on return instructions, as they are control barriers. 2009-11-11 18:11:07 +00:00
SparcISelDAGToDAG.cpp
SparcISelLowering.cpp Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used. 2009-11-23 23:20:51 +00:00
SparcISelLowering.h
SparcMachineFunctionInfo.h
SparcMCAsmInfo.cpp
SparcMCAsmInfo.h
SparcRegisterInfo.cpp Make the MachineFunction argument of getFrameRegister const. 2009-11-12 21:00:03 +00:00
SparcRegisterInfo.h Make the MachineFunction argument of getFrameRegister const. 2009-11-12 21:00:03 +00:00
SparcRegisterInfo.td
SparcSubtarget.cpp
SparcSubtarget.h
SparcTargetMachine.cpp indicate what the native integer types for the target are. 2009-11-07 19:07:32 +00:00
SparcTargetMachine.h

To-do
-----

* Keep the address of the constant pool in a register instead of forming its
  address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
  pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions.  It's
  not clear how to write a pattern for this though:

float %t1(int %a, int* %p) {
        %C = seteq int %a, 0
        br bool %C, label %T, label %F
T:
        store int 123, int* %p
        br label %F
F:
        ret float undef
}

codegens to this:

t1:
        save -96, %o6, %o6
1)      subcc %i0, 0, %l0
1)      bne .LBBt1_2    ! F
        nop
.LBBt1_1:       ! T
        or %g0, 123, %l0
        st %l0, [%i1]
.LBBt1_2:       ! F
        restore %g0, %g0, %g0
        retl
        nop

1) should be replaced with a brz in V9 mode.

* Same as above, but emit conditional move on register zero (p192) in V9 
  mode.  Testcase:

int %t1(int %a, int %b) {
        %C = seteq int %a, 0
        %D = select bool %C, int %a, int %b
        ret int %D
}

* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling 
  with the Y register, if they are faster.

* Codegen bswap(load)/store(bswap) -> load/store ASI

* Implement frame pointer elimination, e.g. eliminate save/restore for 
  leaf fns.
* Fill delay slots