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e9d6f29fb1
Author: obucina Reviewers: dsanders Adds support for third operand for [D]DIV[U] instructions. Additional test for case when destination reg is zero register Differential Revision: http://reviews.llvm.org/D16888 llvm-svn: 269636
19 lines
637 B
ArmAsm
19 lines
637 B
ArmAsm
# RUN: not llvm-mc %s -arch=mips -mcpu=mips32r6 2>&1 | \
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# RUN: FileCheck %s --check-prefix=R6
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# RUN: not llvm-mc %s -arch=mips64 -mcpu=mips64r6 2>&1 | \
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# RUN: FileCheck %s --check-prefix=R6
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# RUN: llvm-mc %s -arch=mips -mcpu=mips32r2 2>&1 | \
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# RUN: FileCheck %s --check-prefix=NOT-R6
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# RUN: llvm-mc %s -arch=mips64 -mcpu=mips64r2 2>&1 | \
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# RUN: FileCheck %s --check-prefix=NOT-R6
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.text
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div $25, $11
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# R6: :[[@LINE-1]]:3: error: instruction requires a CPU feature not currently enabled
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div $25, $0
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# NOT-R6: :[[@LINE-1]]:3: warning: division by zero
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div $0,$0
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# NOT-R6: :[[@LINE-1]]:3: warning: dividing zero by zero
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