RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-12-11 21:45:16 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
f0a90b93e6
llvm-mirror/test/MC/Mips/mips64r5
History
Simon Dardis f137c531a9 [mips] seb, seh instruction aliases 
Add the single operand form.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D26961

llvm-svn: 287681
2016-11-22 19:17:23 +00:00
..
abi-bad.s [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
abiflags.s [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
invalid-mips64.s
invalid-mips64r2.s
invalid-mips64r3.s
invalid.s [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
valid-xfail.s Recommit: "[mips] Add rsqrt, recip for MIPS" 2016-10-05 16:11:01 +00:00
valid.s [mips] seb, seh instruction aliases 2016-11-22 19:17:23 +00:00