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62 lines
2.1 KiB
C++
62 lines
2.1 KiB
C++
//===- ARMInstrInfo.h - ARM Instruction Information -------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the ARM implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMINSTRUCTIONINFO_H
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#define ARMINSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "ARMBaseInstrInfo.h"
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#include "ARMRegisterInfo.h"
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#include "ARMSubtarget.h"
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#include "ARM.h"
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namespace llvm {
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class ARMSubtarget;
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class ARMInstrInfo : public ARMBaseInstrInfo {
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ARMRegisterInfo RI;
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public:
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explicit ARMInstrInfo(const ARMSubtarget &STI);
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// Return the non-pre/post incrementing version of 'Opc'. Return 0
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// if there is not such an opcode.
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unsigned getUnindexedOpcode(unsigned Opc) const;
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// Return the opcode that implements 'Op', or 0 if no opcode
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unsigned getOpcode(ARMII::Op Op) const;
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// If 'opcode' is an instruction with an unsigned offset that also
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// has a version with a signed offset, return the opcode for the
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// version with the signed offset. In 'NumBits' return the number of
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// bits for the signed offset.
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unsigned unsignedOffsetOpcodeToSigned(unsigned opcode,
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unsigned *NumBits) const;
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// Return true if the block does not fall through.
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bool BlockHasNoFallThrough(const MachineBasicBlock &MBB) const;
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const ARMRegisterInfo &getRegisterInfo() const { return RI; }
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void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SubIdx,
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const MachineInstr *Orig) const;
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};
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}
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#endif
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