mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-02-04 11:17:31 +00:00
1701d245d4
Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
11 lines
399 B
ArmAsm
11 lines
399 B
ArmAsm
# Instructions that are invalid
|
|
#
|
|
# RUN: not llvm-mc %s -triple=mips64-unknown-linux -show-encoding \
|
|
# RUN: -mcpu=mips32r5 2>%t1
|
|
# RUN: FileCheck %s < %t1
|
|
|
|
.set noat
|
|
dsbh $v1,$t6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
|
dshd $v0,$sp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
|
|
|