Hal Finkel fa0f576b41 [PowerPC] Add support for the CMPB instruction ... Newer POWER cores, and the A2, support the cmpb instruction. This instruction compares its operands, treating each of the 8 bytes in the GPRs separately, returning a 'mask' result of 0 (for false) or -1 (for true) in each byte. Code generation support is added, in the form of a PPCISelDAGToDAG DAG-preprocessing routine, that recognizes patterns close to what the instruction computes (either exactly, or related by a constant masking operation), and generates the cmpb instruction (along with any necessary constant masking operation). This can be expanded if use cases arise. llvm-svn: 225106		2015-01-03 01:16:37 +00:00
..
AArch64
ARM	Add support for ARM modified-immediate assembly syntax.	2014-12-02 10:53:20 +00:00
Hexagon	[Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation.	2014-12-31 00:08:34 +00:00
Mips	[mips][microMIPS] Implement CACHE, PREF, SSNOP, EHB and PAUSE instructions	2014-12-23 19:55:34 +00:00
PowerPC	[PowerPC] Add support for the CMPB instruction	2015-01-03 01:16:37 +00:00
Sparc
SystemZ
X86	[X86] Disassembler support for move to/from %rax with a 32-bit memory offset is REX.W and AdSize prefix are both present.	2015-01-03 00:00:20 +00:00
XCore