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730 lines
26 KiB
C++
730 lines
26 KiB
C++
//===-- X86/X86CodeEmitter.cpp - Convert X86 code to machine code ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the pass that transforms the X86 machine instructions into
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// relocatable machine code.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "x86-emitter"
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#include "X86InstrInfo.h"
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#include "X86JITInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "X86Relocations.h"
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#include "X86.h"
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#include "llvm/PassManager.h"
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#include "llvm/CodeGen/MachineCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Function.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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STATISTIC(NumEmitted, "Number of machine instructions emitted");
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namespace {
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class VISIBILITY_HIDDEN Emitter : public MachineFunctionPass {
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const X86InstrInfo *II;
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const TargetData *TD;
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X86TargetMachine &TM;
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MachineCodeEmitter &MCE;
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intptr_t PICBaseOffset;
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bool Is64BitMode;
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bool IsPIC;
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public:
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static char ID;
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explicit Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce)
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: MachineFunctionPass(&ID), II(0), TD(0), TM(tm),
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MCE(mce), PICBaseOffset(0), Is64BitMode(false),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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Emitter(X86TargetMachine &tm, MachineCodeEmitter &mce,
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const X86InstrInfo &ii, const TargetData &td, bool is64)
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: MachineFunctionPass(&ID), II(&ii), TD(&td), TM(tm),
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MCE(mce), PICBaseOffset(0), Is64BitMode(is64),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
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bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "X86 Machine Code Emitter";
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}
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void emitInstruction(const MachineInstr &MI,
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const TargetInstrDesc *Desc);
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineModuleInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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private:
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void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
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void emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
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int Disp = 0, intptr_t PCAdj = 0,
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bool NeedStub = false, bool IsLazy = false);
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void emitExternalSymbolAddress(const char *ES, unsigned Reloc);
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void emitConstPoolAddress(unsigned CPI, unsigned Reloc, int Disp = 0,
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intptr_t PCAdj = 0);
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void emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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intptr_t PCAdj = 0);
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void emitDisplacementField(const MachineOperand *RelocOp, int DispVal,
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intptr_t PCAdj = 0);
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void emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeField);
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void emitRegModRMByte(unsigned RegOpcodeField);
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void emitSIBByte(unsigned SS, unsigned Index, unsigned Base);
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void emitConstant(uint64_t Val, unsigned Size);
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void emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField,
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intptr_t PCAdj = 0);
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unsigned getX86RegNum(unsigned RegNo) const;
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bool gvNeedsLazyPtr(const GlobalValue *GV);
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};
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char Emitter::ID = 0;
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}
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/// createX86CodeEmitterPass - Return a pass that emits the collected X86 code
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/// to the specified MCE object.
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FunctionPass *llvm::createX86CodeEmitterPass(X86TargetMachine &TM,
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MachineCodeEmitter &MCE) {
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return new Emitter(TM, MCE);
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}
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bool Emitter::runOnMachineFunction(MachineFunction &MF) {
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MCE.setModuleInfo(&getAnalysis<MachineModuleInfo>());
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II = TM.getInstrInfo();
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TD = TM.getTargetData();
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Is64BitMode = TM.getSubtarget<X86Subtarget>().is64Bit();
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IsPIC = TM.getRelocationModel() == Reloc::PIC_;
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do {
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DOUT << "JITTing function '" << MF.getFunction()->getName() << "'\n";
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MCE.startFunction(MF);
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for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
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MBB != E; ++MBB) {
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MCE.StartMachineBasicBlock(MBB);
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for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
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I != E; ++I) {
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const TargetInstrDesc &Desc = I->getDesc();
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emitInstruction(*I, &Desc);
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// MOVPC32r is basically a call plus a pop instruction.
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if (Desc.getOpcode() == X86::MOVPC32r)
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emitInstruction(*I, &II->get(X86::POP32r));
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NumEmitted++; // Keep track of the # of mi's emitted
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}
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}
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} while (MCE.finishFunction(MF));
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return false;
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}
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/// emitPCRelativeBlockAddress - This method keeps track of the information
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/// necessary to resolve the address of this block later and emits a dummy
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/// value.
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///
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void Emitter::emitPCRelativeBlockAddress(MachineBasicBlock *MBB) {
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// Remember where this reference was and where it is to so we can
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// deal with it later.
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MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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X86::reloc_pcrel_word, MBB));
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MCE.emitWordLE(0);
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}
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/// emitGlobalAddress - Emit the specified address to the code stream assuming
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/// this is part of a "take the address of a global" instruction.
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///
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void Emitter::emitGlobalAddress(GlobalValue *GV, unsigned Reloc,
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int Disp /* = 0 */, intptr_t PCAdj /* = 0 */,
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bool NeedStub /* = false */,
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bool isLazy /* = false */) {
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intptr_t RelocCST = 0;
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if (Reloc == X86::reloc_picrel_word)
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RelocCST = PICBaseOffset;
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else if (Reloc == X86::reloc_pcrel_word)
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RelocCST = PCAdj;
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MachineRelocation MR = isLazy
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? MachineRelocation::getGVLazyPtr(MCE.getCurrentPCOffset(), Reloc,
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GV, RelocCST, NeedStub)
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: MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
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GV, RelocCST, NeedStub);
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MCE.addRelocation(MR);
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
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}
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/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitExternalSymbolAddress(const char *ES, unsigned Reloc) {
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intptr_t RelocCST = (Reloc == X86::reloc_picrel_word) ? PICBaseOffset : 0;
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MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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Reloc, ES, RelocCST));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(0);
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}
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/// emitConstPoolAddress - Arrange for the address of an constant pool
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/// to be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc,
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int Disp /* = 0 */,
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intptr_t PCAdj /* = 0 */) {
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intptr_t RelocCST = 0;
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if (Reloc == X86::reloc_picrel_word)
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RelocCST = PICBaseOffset;
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else if (Reloc == X86::reloc_pcrel_word)
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RelocCST = PCAdj;
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MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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Reloc, CPI, RelocCST));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(Disp); // The relocated value will be added to the displacement
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}
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/// emitJumpTableAddress - Arrange for the address of a jump table to
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/// be emitted to the current location in the function, and allow it to be PC
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/// relative.
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void Emitter::emitJumpTableAddress(unsigned JTI, unsigned Reloc,
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intptr_t PCAdj /* = 0 */) {
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intptr_t RelocCST = 0;
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if (Reloc == X86::reloc_picrel_word)
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RelocCST = PICBaseOffset;
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else if (Reloc == X86::reloc_pcrel_word)
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RelocCST = PCAdj;
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MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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Reloc, JTI, RelocCST));
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if (Reloc == X86::reloc_absolute_dword)
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MCE.emitWordLE(0);
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MCE.emitWordLE(0); // The relocated value will be added to the displacement
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}
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unsigned Emitter::getX86RegNum(unsigned RegNo) const {
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return II->getRegisterInfo().getX86RegNum(RegNo);
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}
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inline static unsigned char ModRMByte(unsigned Mod, unsigned RegOpcode,
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unsigned RM) {
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assert(Mod < 4 && RegOpcode < 8 && RM < 8 && "ModRM Fields out of range!");
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return RM | (RegOpcode << 3) | (Mod << 6);
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}
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void Emitter::emitRegModRMByte(unsigned ModRMReg, unsigned RegOpcodeFld){
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, getX86RegNum(ModRMReg)));
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}
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void Emitter::emitRegModRMByte(unsigned RegOpcodeFld) {
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MCE.emitByte(ModRMByte(3, RegOpcodeFld, 0));
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}
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void Emitter::emitSIBByte(unsigned SS, unsigned Index, unsigned Base) {
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// SIB byte is in the same format as the ModRMByte...
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MCE.emitByte(ModRMByte(SS, Index, Base));
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}
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void Emitter::emitConstant(uint64_t Val, unsigned Size) {
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// Output the constant in little endian byte order...
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for (unsigned i = 0; i != Size; ++i) {
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MCE.emitByte(Val & 255);
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Val >>= 8;
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}
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}
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/// isDisp8 - Return true if this signed displacement fits in a 8-bit
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/// sign-extended field.
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static bool isDisp8(int Value) {
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return Value == (signed char)Value;
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}
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bool Emitter::gvNeedsLazyPtr(const GlobalValue *GV) {
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// For Darwin, simulate the linktime GOT by using the same lazy-pointer
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// mechanism as 32-bit mode.
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return (!Is64BitMode || TM.getSubtarget<X86Subtarget>().isTargetDarwin()) &&
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TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false);
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}
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void Emitter::emitDisplacementField(const MachineOperand *RelocOp,
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int DispVal, intptr_t PCAdj) {
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// If this is a simple integer displacement that doesn't require a relocation,
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// emit it now.
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if (!RelocOp) {
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emitConstant(DispVal, 4);
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return;
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}
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// Otherwise, this is something that requires a relocation. Emit it as such
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// now.
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if (RelocOp->isGlobal()) {
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// In 64-bit static small code model, we could potentially emit absolute.
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// But it's probably not beneficial.
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// 89 05 00 00 00 00 mov %eax,0(%rip) # PC-relative
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// 89 04 25 00 00 00 00 mov %eax,0x0 # Absolute
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
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: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
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bool NeedStub = isa<Function>(RelocOp->getGlobal());
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bool isLazy = gvNeedsLazyPtr(RelocOp->getGlobal());
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emitGlobalAddress(RelocOp->getGlobal(), rt, RelocOp->getOffset(),
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PCAdj, NeedStub, isLazy);
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} else if (RelocOp->isCPI()) {
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
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emitConstPoolAddress(RelocOp->getIndex(), rt,
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RelocOp->getOffset(), PCAdj);
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} else if (RelocOp->isJTI()) {
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unsigned rt = Is64BitMode ? X86::reloc_pcrel_word : X86::reloc_picrel_word;
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emitJumpTableAddress(RelocOp->getIndex(), rt, PCAdj);
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} else {
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assert(0 && "Unknown value to relocate!");
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}
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}
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void Emitter::emitMemModRMByte(const MachineInstr &MI,
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unsigned Op, unsigned RegOpcodeField,
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intptr_t PCAdj) {
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const MachineOperand &Op3 = MI.getOperand(Op+3);
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int DispVal = 0;
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const MachineOperand *DispForReloc = 0;
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// Figure out what sort of displacement we have to handle here.
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if (Op3.isGlobal()) {
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DispForReloc = &Op3;
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} else if (Op3.isCPI()) {
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if (Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex());
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DispVal += Op3.getOffset();
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}
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} else if (Op3.isJTI()) {
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if (Is64BitMode || IsPIC) {
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DispForReloc = &Op3;
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} else {
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DispVal += MCE.getJumpTableEntryAddress(Op3.getIndex());
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}
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} else {
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DispVal = Op3.getImm();
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}
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const MachineOperand &Base = MI.getOperand(Op);
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const MachineOperand &Scale = MI.getOperand(Op+1);
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const MachineOperand &IndexReg = MI.getOperand(Op+2);
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unsigned BaseReg = Base.getReg();
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// Is a SIB byte needed?
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if (IndexReg.getReg() == 0 &&
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(BaseReg == 0 || getX86RegNum(BaseReg) != N86::ESP)) {
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if (BaseReg == 0) { // Just a displacement?
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// Emit special case [disp32] encoding
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 5));
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emitDisplacementField(DispForReloc, DispVal, PCAdj);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
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// Emit simple indirect register encoding... [EAX] f.e.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, BaseRegNo));
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} else if (!DispForReloc && isDisp8(DispVal)) {
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// Emit the disp8 encoding... [REG+disp8]
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MCE.emitByte(ModRMByte(1, RegOpcodeField, BaseRegNo));
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emitConstant(DispVal, 1);
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} else {
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// Emit the most general non-SIB encoding: [REG+disp32]
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MCE.emitByte(ModRMByte(2, RegOpcodeField, BaseRegNo));
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emitDisplacementField(DispForReloc, DispVal, PCAdj);
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}
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}
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} else { // We need a SIB byte, so start by outputting the ModR/M byte first
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assert(IndexReg.getReg() != X86::ESP &&
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IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
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bool ForceDisp32 = false;
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bool ForceDisp8 = false;
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if (BaseReg == 0) {
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// If there is no base register, we emit the special case SIB byte with
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// MOD=0, BASE=5, to JUST get the index, scale, and displacement.
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (DispForReloc) {
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// Emit the normal disp32 encoding.
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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ForceDisp32 = true;
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} else if (DispVal == 0 && getX86RegNum(BaseReg) != N86::EBP) {
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// Emit no displacement ModR/M byte
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MCE.emitByte(ModRMByte(0, RegOpcodeField, 4));
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} else if (isDisp8(DispVal)) {
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// Emit the disp8 encoding...
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MCE.emitByte(ModRMByte(1, RegOpcodeField, 4));
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ForceDisp8 = true; // Make sure to force 8 bit disp if Base=EBP
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} else {
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// Emit the normal disp32 encoding...
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MCE.emitByte(ModRMByte(2, RegOpcodeField, 4));
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}
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// Calculate what the SS field value should be...
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static const unsigned SSTable[] = { ~0, 0, 1, ~0, 2, ~0, ~0, ~0, 3 };
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unsigned SS = SSTable[Scale.getImm()];
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if (BaseReg == 0) {
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// Handle the SIB byte for the case where there is no base. The
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// displacement has already been output.
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assert(IndexReg.getReg() && "Index register must be specified!");
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emitSIBByte(SS, getX86RegNum(IndexReg.getReg()), 5);
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} else {
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unsigned BaseRegNo = getX86RegNum(BaseReg);
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unsigned IndexRegNo;
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if (IndexReg.getReg())
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IndexRegNo = getX86RegNum(IndexReg.getReg());
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else
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IndexRegNo = 4; // For example [ESP+1*<noreg>+4]
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emitSIBByte(SS, IndexRegNo, BaseRegNo);
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}
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// Do we need to output a displacement?
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if (ForceDisp8) {
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emitConstant(DispVal, 1);
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} else if (DispVal != 0 || ForceDisp32) {
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emitDisplacementField(DispForReloc, DispVal, PCAdj);
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}
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}
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}
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void Emitter::emitInstruction(const MachineInstr &MI,
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const TargetInstrDesc *Desc) {
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DOUT << MI;
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unsigned Opcode = Desc->Opcode;
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// Emit the lock opcode prefix as needed.
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if (Desc->TSFlags & X86II::LOCK) MCE.emitByte(0xF0);
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// Emit segment override opcode prefix as needed.
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switch (Desc->TSFlags & X86II::SegOvrMask) {
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case X86II::FS:
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MCE.emitByte(0x64);
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break;
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case X86II::GS:
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MCE.emitByte(0x65);
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break;
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default: assert(0 && "Invalid segment!");
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case 0: break; // No segment override!
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}
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// Emit the repeat opcode prefix as needed.
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if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) MCE.emitByte(0xF3);
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// Emit the operand size opcode prefix as needed.
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if (Desc->TSFlags & X86II::OpSize) MCE.emitByte(0x66);
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// Emit the address size opcode prefix as needed.
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if (Desc->TSFlags & X86II::AdSize) MCE.emitByte(0x67);
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bool Need0FPrefix = false;
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switch (Desc->TSFlags & X86II::Op0Mask) {
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case X86II::TB: // Two-byte opcode prefix
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case X86II::T8: // 0F 38
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case X86II::TA: // 0F 3A
|
|
Need0FPrefix = true;
|
|
break;
|
|
case X86II::REP: break; // already handled.
|
|
case X86II::XS: // F3 0F
|
|
MCE.emitByte(0xF3);
|
|
Need0FPrefix = true;
|
|
break;
|
|
case X86II::XD: // F2 0F
|
|
MCE.emitByte(0xF2);
|
|
Need0FPrefix = true;
|
|
break;
|
|
case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
|
|
case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
|
|
MCE.emitByte(0xD8+
|
|
(((Desc->TSFlags & X86II::Op0Mask)-X86II::D8)
|
|
>> X86II::Op0Shift));
|
|
break; // Two-byte opcode prefix
|
|
default: assert(0 && "Invalid prefix!");
|
|
case 0: break; // No prefix!
|
|
}
|
|
|
|
if (Is64BitMode) {
|
|
// REX prefix
|
|
unsigned REX = X86InstrInfo::determineREX(MI);
|
|
if (REX)
|
|
MCE.emitByte(0x40 | REX);
|
|
}
|
|
|
|
// 0x0F escape code must be emitted just before the opcode.
|
|
if (Need0FPrefix)
|
|
MCE.emitByte(0x0F);
|
|
|
|
switch (Desc->TSFlags & X86II::Op0Mask) {
|
|
case X86II::T8: // 0F 38
|
|
MCE.emitByte(0x38);
|
|
break;
|
|
case X86II::TA: // 0F 3A
|
|
MCE.emitByte(0x3A);
|
|
break;
|
|
}
|
|
|
|
// If this is a two-address instruction, skip one of the register operands.
|
|
unsigned NumOps = Desc->getNumOperands();
|
|
unsigned CurOp = 0;
|
|
if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
|
|
++CurOp;
|
|
else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
|
|
// Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
|
|
--NumOps;
|
|
|
|
unsigned char BaseOpcode = II->getBaseOpcodeFor(Desc);
|
|
switch (Desc->TSFlags & X86II::FormMask) {
|
|
default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!");
|
|
case X86II::Pseudo:
|
|
// Remember the current PC offset, this is the PIC relocation
|
|
// base address.
|
|
switch (Opcode) {
|
|
default:
|
|
assert(0 && "psuedo instructions should be removed before code emission");
|
|
break;
|
|
case TargetInstrInfo::INLINEASM: {
|
|
const char* Value = MI.getOperand(0).getSymbolName();
|
|
/* We allow inline assembler nodes with empty bodies - they can
|
|
implicitly define registers, which is ok for JIT. */
|
|
assert((Value[0] == 0) && "JIT does not support inline asm!\n");
|
|
break;
|
|
}
|
|
case TargetInstrInfo::DBG_LABEL:
|
|
case TargetInstrInfo::EH_LABEL:
|
|
MCE.emitLabel(MI.getOperand(0).getImm());
|
|
break;
|
|
case TargetInstrInfo::IMPLICIT_DEF:
|
|
case TargetInstrInfo::DECLARE:
|
|
case X86::DWARF_LOC:
|
|
case X86::FP_REG_KILL:
|
|
break;
|
|
case X86::MOVPC32r: {
|
|
// This emits the "call" portion of this pseudo instruction.
|
|
MCE.emitByte(BaseOpcode);
|
|
emitConstant(0, X86InstrInfo::sizeOfImm(Desc));
|
|
// Remember PIC base.
|
|
PICBaseOffset = MCE.getCurrentPCOffset();
|
|
X86JITInfo *JTI = TM.getJITInfo();
|
|
JTI->setPICBase(MCE.getCurrentPCValue());
|
|
break;
|
|
}
|
|
}
|
|
CurOp = NumOps;
|
|
break;
|
|
case X86II::RawFrm:
|
|
MCE.emitByte(BaseOpcode);
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO = MI.getOperand(CurOp++);
|
|
|
|
DOUT << "RawFrm CurOp " << CurOp << "\n";
|
|
DOUT << "isMBB " << MO.isMBB() << "\n";
|
|
DOUT << "isGlobal " << MO.isGlobal() << "\n";
|
|
DOUT << "isSymbol " << MO.isSymbol() << "\n";
|
|
DOUT << "isImm " << MO.isImm() << "\n";
|
|
|
|
if (MO.isMBB()) {
|
|
emitPCRelativeBlockAddress(MO.getMBB());
|
|
} else if (MO.isGlobal()) {
|
|
// Assume undefined functions may be outside the Small codespace.
|
|
bool NeedStub =
|
|
(Is64BitMode &&
|
|
(TM.getCodeModel() == CodeModel::Large ||
|
|
TM.getSubtarget<X86Subtarget>().isTargetDarwin())) ||
|
|
Opcode == X86::TAILJMPd;
|
|
emitGlobalAddress(MO.getGlobal(), X86::reloc_pcrel_word,
|
|
0, 0, NeedStub);
|
|
} else if (MO.isSymbol()) {
|
|
emitExternalSymbolAddress(MO.getSymbolName(), X86::reloc_pcrel_word);
|
|
} else if (MO.isImm()) {
|
|
emitConstant(MO.getImm(), X86InstrInfo::sizeOfImm(Desc));
|
|
} else {
|
|
assert(0 && "Unknown RawFrm operand!");
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86II::AddRegFrm:
|
|
MCE.emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++).getReg()));
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO1 = MI.getOperand(CurOp++);
|
|
unsigned Size = X86InstrInfo::sizeOfImm(Desc);
|
|
if (MO1.isImm())
|
|
emitConstant(MO1.getImm(), Size);
|
|
else {
|
|
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
|
|
: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
|
|
// This should not occur on Darwin for relocatable objects.
|
|
if (Opcode == X86::MOV64ri)
|
|
rt = X86::reloc_absolute_dword; // FIXME: add X86II flag?
|
|
if (MO1.isGlobal()) {
|
|
bool NeedStub = isa<Function>(MO1.getGlobal());
|
|
bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
|
|
emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
|
|
NeedStub, isLazy);
|
|
} else if (MO1.isSymbol())
|
|
emitExternalSymbolAddress(MO1.getSymbolName(), rt);
|
|
else if (MO1.isCPI())
|
|
emitConstPoolAddress(MO1.getIndex(), rt);
|
|
else if (MO1.isJTI())
|
|
emitJumpTableAddress(MO1.getIndex(), rt);
|
|
}
|
|
}
|
|
break;
|
|
|
|
case X86II::MRMDestReg: {
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
|
|
getX86RegNum(MI.getOperand(CurOp+1).getReg()));
|
|
CurOp += 2;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
case X86II::MRMDestMem: {
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, CurOp, getX86RegNum(MI.getOperand(CurOp+4).getReg()));
|
|
CurOp += 5;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
|
|
case X86II::MRMSrcReg:
|
|
MCE.emitByte(BaseOpcode);
|
|
emitRegModRMByte(MI.getOperand(CurOp+1).getReg(),
|
|
getX86RegNum(MI.getOperand(CurOp).getReg()));
|
|
CurOp += 2;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
|
|
break;
|
|
|
|
case X86II::MRMSrcMem: {
|
|
intptr_t PCAdj = (CurOp+5 != NumOps) ? X86InstrInfo::sizeOfImm(Desc) : 0;
|
|
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, CurOp+1, getX86RegNum(MI.getOperand(CurOp).getReg()),
|
|
PCAdj);
|
|
CurOp += 5;
|
|
if (CurOp != NumOps)
|
|
emitConstant(MI.getOperand(CurOp++).getImm(), X86InstrInfo::sizeOfImm(Desc));
|
|
break;
|
|
}
|
|
|
|
case X86II::MRM0r: case X86II::MRM1r:
|
|
case X86II::MRM2r: case X86II::MRM3r:
|
|
case X86II::MRM4r: case X86II::MRM5r:
|
|
case X86II::MRM6r: case X86II::MRM7r: {
|
|
MCE.emitByte(BaseOpcode);
|
|
|
|
// Special handling of lfence and mfence.
|
|
if (Desc->getOpcode() == X86::LFENCE ||
|
|
Desc->getOpcode() == X86::MFENCE)
|
|
emitRegModRMByte((Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
|
|
else
|
|
emitRegModRMByte(MI.getOperand(CurOp++).getReg(),
|
|
(Desc->TSFlags & X86II::FormMask)-X86II::MRM0r);
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO1 = MI.getOperand(CurOp++);
|
|
unsigned Size = X86InstrInfo::sizeOfImm(Desc);
|
|
if (MO1.isImm())
|
|
emitConstant(MO1.getImm(), Size);
|
|
else {
|
|
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
|
|
: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
|
|
if (Opcode == X86::MOV64ri32)
|
|
rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
|
|
if (MO1.isGlobal()) {
|
|
bool NeedStub = isa<Function>(MO1.getGlobal());
|
|
bool isLazy = gvNeedsLazyPtr(MO1.getGlobal());
|
|
emitGlobalAddress(MO1.getGlobal(), rt, MO1.getOffset(), 0,
|
|
NeedStub, isLazy);
|
|
} else if (MO1.isSymbol())
|
|
emitExternalSymbolAddress(MO1.getSymbolName(), rt);
|
|
else if (MO1.isCPI())
|
|
emitConstPoolAddress(MO1.getIndex(), rt);
|
|
else if (MO1.isJTI())
|
|
emitJumpTableAddress(MO1.getIndex(), rt);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case X86II::MRM0m: case X86II::MRM1m:
|
|
case X86II::MRM2m: case X86II::MRM3m:
|
|
case X86II::MRM4m: case X86II::MRM5m:
|
|
case X86II::MRM6m: case X86II::MRM7m: {
|
|
intptr_t PCAdj = (CurOp+4 != NumOps) ?
|
|
(MI.getOperand(CurOp+4).isImm() ? X86InstrInfo::sizeOfImm(Desc) : 4) : 0;
|
|
|
|
MCE.emitByte(BaseOpcode);
|
|
emitMemModRMByte(MI, CurOp, (Desc->TSFlags & X86II::FormMask)-X86II::MRM0m,
|
|
PCAdj);
|
|
CurOp += 4;
|
|
|
|
if (CurOp != NumOps) {
|
|
const MachineOperand &MO = MI.getOperand(CurOp++);
|
|
unsigned Size = X86InstrInfo::sizeOfImm(Desc);
|
|
if (MO.isImm())
|
|
emitConstant(MO.getImm(), Size);
|
|
else {
|
|
unsigned rt = Is64BitMode ? X86::reloc_pcrel_word
|
|
: (IsPIC ? X86::reloc_picrel_word : X86::reloc_absolute_word);
|
|
if (Opcode == X86::MOV64mi32)
|
|
rt = X86::reloc_absolute_word; // FIXME: add X86II flag?
|
|
if (MO.isGlobal()) {
|
|
bool NeedStub = isa<Function>(MO.getGlobal());
|
|
bool isLazy = gvNeedsLazyPtr(MO.getGlobal());
|
|
emitGlobalAddress(MO.getGlobal(), rt, MO.getOffset(), 0,
|
|
NeedStub, isLazy);
|
|
} else if (MO.isSymbol())
|
|
emitExternalSymbolAddress(MO.getSymbolName(), rt);
|
|
else if (MO.isCPI())
|
|
emitConstPoolAddress(MO.getIndex(), rt);
|
|
else if (MO.isJTI())
|
|
emitJumpTableAddress(MO.getIndex(), rt);
|
|
}
|
|
}
|
|
break;
|
|
}
|
|
|
|
case X86II::MRMInitReg:
|
|
MCE.emitByte(BaseOpcode);
|
|
// Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
|
|
emitRegModRMByte(MI.getOperand(CurOp).getReg(),
|
|
getX86RegNum(MI.getOperand(CurOp).getReg()));
|
|
++CurOp;
|
|
break;
|
|
}
|
|
|
|
if (!Desc->isVariadic() && CurOp != NumOps) {
|
|
cerr << "Cannot encode: ";
|
|
MI.dump();
|
|
cerr << '\n';
|
|
abort();
|
|
}
|
|
}
|