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- CodeGenPrepare pass for identifying div/rem ops - Backend specifies the type mapping using addBypassSlowDivType - Enabled only for Intel Atom with O2 32-bit -> 8-bit - Replace IDIV with instructions which test its value and use DIVB if the value is positive and less than 256. - In the case when the quotient and remainder of a divide are used a DIV and a REM instruction will be present in the IR. In the non-Atom case they are both lowered to IDIVs and CSE removes the redundant IDIV instruction, using the quotient and remainder from the first IDIV. However, due to this optimization CSE is not able to eliminate redundant IDIV instructions because they are located in different basic blocks. This is overcome by calculating both the quotient (DIV) and remainder (REM) in each basic block that is inserted by the optimization and reusing the result values when a subsequent DIV or REM instruction uses the same operands. - Test cases check for the presents of the optimization when calculating either the quotient, remainder, or both. Patch by Tyler Nowicki! llvm-svn: 163150 |
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| .. | ||
| Mangler.h | ||
| Target.td | ||
| TargetCallingConv.h | ||
| TargetCallingConv.td | ||
| TargetData.h | ||
| TargetELFWriterInfo.h | ||
| TargetFrameLowering.h | ||
| TargetInstrInfo.h | ||
| TargetIntrinsicInfo.h | ||
| TargetItinerary.td | ||
| TargetJITInfo.h | ||
| TargetLibraryInfo.h | ||
| TargetLowering.h | ||
| TargetLoweringObjectFile.h | ||
| TargetMachine.h | ||
| TargetOpcodes.h | ||
| TargetOptions.h | ||
| TargetRegisterInfo.h | ||
| TargetSchedule.td | ||
| TargetSelectionDAG.td | ||
| TargetSelectionDAGInfo.h | ||
| TargetSubtargetInfo.h | ||