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PredicateInstruction returns true if the operation was successful.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37124 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-05-16 21:53:07 +00:00
parent 2eb80fa433
commit 02c602b333
4 changed files with 29 additions and 20 deletions
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4
include/llvm/Target/TargetInstrInfo.h
View File

@ -390,8 +390,8 @@ public:
}
/// PredicateInstruction - Convert the instruction into a predicated
/// instruction.
virtual void PredicateInstruction(MachineInstr *MI,
/// instruction. It returns true if the operation was successful.
virtual bool PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const;
/// getPointerRegClass - Returns a TargetRegisterClass used for pointer

10
lib/Target/ARM/ARMInstrInfo.cpp
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@ -423,17 +423,21 @@ ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
return false;
}
void ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
bool ARMInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const {
unsigned Opc = MI->getOpcode();
if (Opc == ARM::B || Opc == ARM::tB) {
MI->setInstrDescriptor(get(Opc == ARM::B ? ARM::Bcc : ARM::tBcc));
MI->addImmOperand(Cond[0].getImmedValue());
return;
return true;
}
MachineOperand *PMO = MI->findFirstPredOperand();
PMO->setImm(Cond[0].getImmedValue());
if (PMO) {
PMO->setImm(Cond[0].getImmedValue());
return true;
}
return false;
}

2
lib/Target/ARM/ARMInstrInfo.h
View File

@ -104,7 +104,7 @@ public:
virtual bool ReverseBranchCondition(std::vector<MachineOperand> &Cond) const;
// Predication support.
virtual void PredicateInstruction(MachineInstr *MI,
virtual bool PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const;
};

33
lib/Target/TargetInstrInfo.cpp
View File

@ -60,22 +60,27 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
return MI;
}
void TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
std::vector<MachineOperand> &Cond) const {
bool MadeChange = false;
const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
assert((TID->Flags & M_PREDICABLE) &&
"Predicating an unpredicable instruction!");
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg())
MO.setReg(Cond[j].getReg());
else if (MO.isImm())
MO.setImm(Cond[j].getImmedValue());
else if (MO.isMBB())
MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
++j;
if (TID->Flags & M_PREDICABLE) {
for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isReg()) {
MO.setReg(Cond[j].getReg());
MadeChange = true;
} else if (MO.isImm()) {
MO.setImm(Cond[j].getImmedValue());
MadeChange = true;
} else if (MO.isMBB()) {
MO.setMachineBasicBlock(Cond[j].getMachineBasicBlock());
MadeChange = true;
}
++j;
}
}
}
return MadeChange;
}