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test/CodeGen/X86: Relax test case

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No need to hardcode register or expecting totally unnecessary spills
from the allocator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@346575 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matthias Braun
2018-11-10 00:34:09 +00:00
parent bc177f5fc7
commit 02fce9c9ac
1 changed files with 4 additions and 6 deletions
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test/CodeGen/X86/2009-04-12-FastIselOverflowCrash.ll
+4 -6
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@@ -12,12 +12,10 @@ define fastcc i32 @test() nounwind {
entry:
; CHECK-LABEL: test:
; CHECK: ## %bb.0:
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: addl $0, %eax
; CHECK-NEXT: seto %cl
; CHECK-NEXT: movl %eax, -{{[0-9]+}}(%rsp) ## 4-byte Spill
; CHECK-NEXT: movb %cl, -{{[0-9]+}}(%rsp) ## 1-byte Spill
; CHECK-NEXT: jo LBB0_2
; CHECK-NEXT: movl $1, [[REG:%e[a-z]+]]
; CHECK-NEXT: addl $0, [[REG]]
; CHECK-NEXT: seto {{%[a-z]+l}}
; CHECK: jo LBB0_2
%tmp1 = call %0 @llvm.sadd.with.overflow.i32(i32 1, i32 0)
%tmp2 = extractvalue %0 %tmp1, 1
br i1 %tmp2, label %.backedge, label %BB3