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AMDGPU: Fix SMEM WAR hazard for gfx10 readlane

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Summary: Hazard recognizer fails to see hazard with V_READLANE_B32_gfx10.

Reviewers: rampitec

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D69172

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Austin Kerbow
2019-10-18 18:20:30 +00:00
parent ba0c352c6a
commit 0a8dc0861b
2 changed files with 16 additions and 0 deletions
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lib/Target/AMDGPU/GCNHazardRecognizer.cpp
+1
View File
@@ -952,6 +952,7 @@ bool GCNHazardRecognizer::fixSMEMtoVectorWriteHazards(MachineInstr *MI) {
unsigned SDSTName;
switch (MI->getOpcode()) {
case AMDGPU::V_READLANE_B32:
case AMDGPU::V_READLANE_B32_gfx10:
case AMDGPU::V_READFIRSTLANE_B32:
SDSTName = AMDGPU::OpName::vdst;
break;
test/CodeGen/AMDGPU/smem-war-hazard.mir
+15
View File
@@ -304,6 +304,21 @@ body: |
S_ENDPGM 0
...
# Workaround since spilling/restoring SGPRs use real opcodes.
# GCN-LABEL: name: hazard_smem_war_readlane_gfx10
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0
# GCN-NEXT: V_READLANE_B32_gfx10
---
name: hazard_smem_war_readlane_gfx10
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr3, $vgpr0
$sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0, 0
$sgpr0 = V_READLANE_B32_gfx10 $vgpr0, $sgpr3
S_ENDPGM 0
...
# GCN-LABEL: name: hazard_smem_war_readfirstlane
# GCN: S_LOAD_DWORD_IMM
# GCN: $sgpr_null = S_MOV_B32 0