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AMDGPU/GlobalISel: Rename MIRBuilder to B. NFC
Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67374 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@371467 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Austin Kerbow
@@ -31,9 +31,9 @@ using namespace llvm;
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namespace {
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struct OutgoingValueHandler : public CallLowering::ValueHandler {
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OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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OutgoingValueHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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MachineInstrBuilder MIB, CCAssignFn *AssignFn)
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: ValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB) {}
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: ValueHandler(B, MRI, AssignFn), MIB(MIB) {}
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MachineInstrBuilder MIB;
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@@ -73,9 +73,9 @@ struct OutgoingValueHandler : public CallLowering::ValueHandler {
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struct IncomingArgHandler : public CallLowering::ValueHandler {
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uint64_t StackUsed = 0;
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IncomingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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IncomingArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: ValueHandler(MIRBuilder, MRI, AssignFn) {}
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: ValueHandler(B, MRI, AssignFn) {}
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Register getStackAddress(uint64_t Size, int64_t Offset,
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MachinePointerInfo &MPO) override {
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@@ -133,9 +133,9 @@ struct IncomingArgHandler : public CallLowering::ValueHandler {
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};
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struct FormalArgHandler : public IncomingArgHandler {
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FormalArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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FormalArgHandler(MachineIRBuilder &B, MachineRegisterInfo &MRI,
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CCAssignFn *AssignFn)
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: IncomingArgHandler(MIRBuilder, MRI, AssignFn) {}
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: IncomingArgHandler(B, MRI, AssignFn) {}
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void markPhysRegUsed(unsigned PhysReg) override {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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@@ -213,14 +213,14 @@ static LLT getMultipleType(LLT OrigTy, int Factor) {
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}
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// TODO: Move to generic code
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static void unpackRegsToOrigType(MachineIRBuilder &MIRBuilder,
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static void unpackRegsToOrigType(MachineIRBuilder &B,
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ArrayRef<Register> DstRegs,
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Register SrcReg,
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LLT SrcTy,
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LLT PartTy) {
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assert(DstRegs.size() > 1 && "Nothing to unpack");
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFunction &MF = B.getMF();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const unsigned SrcSize = SrcTy.getSizeInBits();
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@@ -229,40 +229,40 @@ static void unpackRegsToOrigType(MachineIRBuilder &MIRBuilder,
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if (SrcTy.isVector() && !PartTy.isVector() &&
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PartSize > SrcTy.getElementType().getSizeInBits()) {
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// Vector was scalarized, and the elements extended.
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auto UnmergeToEltTy = MIRBuilder.buildUnmerge(SrcTy.getElementType(),
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auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(),
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SrcReg);
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for (int i = 0, e = DstRegs.size(); i != e; ++i)
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MIRBuilder.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
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B.buildAnyExt(DstRegs[i], UnmergeToEltTy.getReg(i));
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return;
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}
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if (SrcSize % PartSize == 0) {
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MIRBuilder.buildUnmerge(DstRegs, SrcReg);
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B.buildUnmerge(DstRegs, SrcReg);
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return;
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}
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const int NumRoundedParts = (SrcSize + PartSize - 1) / PartSize;
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LLT BigTy = getMultipleType(PartTy, NumRoundedParts);
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auto ImpDef = MIRBuilder.buildUndef(BigTy);
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auto ImpDef = B.buildUndef(BigTy);
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Register BigReg = MRI.createGenericVirtualRegister(BigTy);
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MIRBuilder.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
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B.buildInsert(BigReg, ImpDef.getReg(0), SrcReg, 0).getReg(0);
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int64_t Offset = 0;
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for (unsigned i = 0, e = DstRegs.size(); i != e; ++i, Offset += PartSize)
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MIRBuilder.buildExtract(DstRegs[i], BigReg, Offset);
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B.buildExtract(DstRegs[i], BigReg, Offset);
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}
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/// Lower the return value for the already existing \p Ret. This assumes that
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/// \p MIRBuilder's insertion point is correct.
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bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
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/// \p B's insertion point is correct.
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bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &B,
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const Value *Val, ArrayRef<Register> VRegs,
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MachineInstrBuilder &Ret) const {
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if (!Val)
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return true;
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auto &MF = MIRBuilder.getMF();
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auto &MF = B.getMF();
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const auto &F = MF.getFunction();
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const DataLayout &DL = MF.getDataLayout();
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@@ -277,69 +277,69 @@ bool AMDGPUCallLowering::lowerReturnVal(MachineIRBuilder &MIRBuilder,
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splitToValueTypes(
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OrigRetInfo, SplitRetInfos, DL, MRI, CC,
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[&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) {
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unpackRegsToOrigType(MIRBuilder, Regs, VRegs[VTSplitIdx], LLTy, PartLLT);
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unpackRegsToOrigType(B, Regs, VRegs[VTSplitIdx], LLTy, PartLLT);
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});
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CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(CC, F.isVarArg());
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OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret, AssignFn);
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return handleAssignments(MIRBuilder, SplitRetInfos, RetHandler);
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OutgoingValueHandler RetHandler(B, MF.getRegInfo(), Ret, AssignFn);
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return handleAssignments(B, SplitRetInfos, RetHandler);
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}
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bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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bool AMDGPUCallLowering::lowerReturn(MachineIRBuilder &B,
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const Value *Val,
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ArrayRef<Register> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFunction &MF = B.getMF();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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MFI->setIfReturnsVoid(!Val);
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assert(!Val == VRegs.empty() && "Return value without a vreg");
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CallingConv::ID CC = MIRBuilder.getMF().getFunction().getCallingConv();
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CallingConv::ID CC = B.getMF().getFunction().getCallingConv();
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const bool IsShader = AMDGPU::isShader(CC);
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const bool IsWaveEnd = (IsShader && MFI->returnsVoid()) ||
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AMDGPU::isKernel(CC);
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if (IsWaveEnd) {
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MIRBuilder.buildInstr(AMDGPU::S_ENDPGM)
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B.buildInstr(AMDGPU::S_ENDPGM)
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.addImm(0);
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return true;
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}
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auto const &ST = MIRBuilder.getMF().getSubtarget<GCNSubtarget>();
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auto const &ST = B.getMF().getSubtarget<GCNSubtarget>();
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unsigned ReturnOpc =
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IsShader ? AMDGPU::SI_RETURN_TO_EPILOG : AMDGPU::S_SETPC_B64_return;
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auto Ret = MIRBuilder.buildInstrNoInsert(ReturnOpc);
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auto Ret = B.buildInstrNoInsert(ReturnOpc);
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Register ReturnAddrVReg;
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if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
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ReturnAddrVReg = MRI.createVirtualRegister(&AMDGPU::CCR_SGPR_64RegClass);
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Ret.addUse(ReturnAddrVReg);
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}
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if (!lowerReturnVal(MIRBuilder, Val, VRegs, Ret))
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if (!lowerReturnVal(B, Val, VRegs, Ret))
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return false;
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if (ReturnOpc == AMDGPU::S_SETPC_B64_return) {
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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Register LiveInReturn = MF.addLiveIn(TRI->getReturnAddressReg(MF),
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&AMDGPU::SGPR_64RegClass);
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MIRBuilder.buildCopy(ReturnAddrVReg, LiveInReturn);
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B.buildCopy(ReturnAddrVReg, LiveInReturn);
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}
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// TODO: Handle CalleeSavedRegsViaCopy.
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MIRBuilder.insertInstr(Ret);
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B.insertInstr(Ret);
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return true;
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}
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Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
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Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &B,
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Type *ParamTy,
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uint64_t Offset) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFunction &MF = B.getMF();
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const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const Function &F = MF.getFunction();
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@@ -352,24 +352,24 @@ Register AMDGPUCallLowering::lowerParameterPtr(MachineIRBuilder &MIRBuilder,
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Register KernArgSegmentVReg = MRI.getLiveInVirtReg(KernArgSegmentPtr);
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Register OffsetReg = MRI.createGenericVirtualRegister(LLT::scalar(64));
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MIRBuilder.buildConstant(OffsetReg, Offset);
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B.buildConstant(OffsetReg, Offset);
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MIRBuilder.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
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B.buildGEP(DstReg, KernArgSegmentVReg, OffsetReg);
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return DstReg;
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}
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void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
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void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &B,
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Type *ParamTy, uint64_t Offset,
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unsigned Align,
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Register DstReg) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFunction &MF = B.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = F.getParent()->getDataLayout();
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PointerType *PtrTy = PointerType::get(ParamTy, AMDGPUAS::CONSTANT_ADDRESS);
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MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
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unsigned TypeSize = DL.getTypeStoreSize(ParamTy);
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Register PtrReg = lowerParameterPtr(MIRBuilder, ParamTy, Offset);
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Register PtrReg = lowerParameterPtr(B, ParamTy, Offset);
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MachineMemOperand *MMO =
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MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad |
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@@ -377,12 +377,12 @@ void AMDGPUCallLowering::lowerParameter(MachineIRBuilder &MIRBuilder,
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MachineMemOperand::MOInvariant,
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TypeSize, Align);
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MIRBuilder.buildLoad(DstReg, PtrReg, *MMO);
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B.buildLoad(DstReg, PtrReg, *MMO);
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}
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// Allocate special inputs passed in user SGPRs.
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static void allocateHSAUserSGPRs(CCState &CCInfo,
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MachineIRBuilder &MIRBuilder,
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MachineIRBuilder &B,
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MachineFunction &MF,
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const SIRegisterInfo &TRI,
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SIMachineFunctionInfo &Info) {
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@@ -411,8 +411,8 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
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const LLT P4 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
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Register VReg = MRI.createGenericVirtualRegister(P4);
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MRI.addLiveIn(InputPtrReg, VReg);
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MIRBuilder.getMBB().addLiveIn(InputPtrReg);
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MIRBuilder.buildCopy(VReg, InputPtrReg);
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B.getMBB().addLiveIn(InputPtrReg);
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B.buildCopy(VReg, InputPtrReg);
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CCInfo.AllocateReg(InputPtrReg);
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}
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@@ -433,9 +433,9 @@ static void allocateHSAUserSGPRs(CCState &CCInfo,
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}
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bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
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MachineIRBuilder &MIRBuilder, const Function &F,
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MachineIRBuilder &B, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs) const {
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MachineFunction &MF = MIRBuilder.getMF();
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MachineFunction &MF = B.getMF();
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const GCNSubtarget *Subtarget = &MF.getSubtarget<GCNSubtarget>();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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@@ -447,7 +447,7 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
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SmallVector<CCValAssign, 16> ArgLocs;
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CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext());
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allocateHSAUserSGPRs(CCInfo, MIRBuilder, MF, *TRI, *Info);
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allocateHSAUserSGPRs(CCInfo, B, MF, *TRI, *Info);
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unsigned i = 0;
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const unsigned KernArgBaseAlign = 16;
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@@ -473,9 +473,9 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
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: MRI.createGenericVirtualRegister(getLLTForType(*ArgTy, DL));
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unsigned Align = MinAlign(KernArgBaseAlign, ArgOffset);
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ArgOffset = alignTo(ArgOffset, DL.getABITypeAlignment(ArgTy));
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lowerParameter(MIRBuilder, ArgTy, ArgOffset, Align, ArgReg);
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lowerParameter(B, ArgTy, ArgOffset, Align, ArgReg);
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if (OrigArgRegs.size() > 1)
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unpackRegs(OrigArgRegs, ArgReg, ArgTy, MIRBuilder);
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unpackRegs(OrigArgRegs, ArgReg, ArgTy, B);
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++i;
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}
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@@ -485,13 +485,13 @@ bool AMDGPUCallLowering::lowerFormalArgumentsKernel(
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}
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// TODO: Move this to generic code
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static void packSplitRegsToOrigType(MachineIRBuilder &MIRBuilder,
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static void packSplitRegsToOrigType(MachineIRBuilder &B,
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ArrayRef<Register> OrigRegs,
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ArrayRef<Register> Regs,
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LLT LLTy,
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LLT PartLLT) {
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if (!LLTy.isVector() && !PartLLT.isVector()) {
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MIRBuilder.buildMerge(OrigRegs[0], Regs);
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B.buildMerge(OrigRegs[0], Regs);
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return;
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}
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@@ -501,15 +501,15 @@ static void packSplitRegsToOrigType(MachineIRBuilder &MIRBuilder,
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int DstElts = LLTy.getNumElements();
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int PartElts = PartLLT.getNumElements();
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if (DstElts % PartElts == 0)
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MIRBuilder.buildConcatVectors(OrigRegs[0], Regs);
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B.buildConcatVectors(OrigRegs[0], Regs);
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else {
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// Deal with v3s16 split into v2s16
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assert(PartElts == 2 && DstElts % 2 != 0);
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int RoundedElts = PartElts * ((DstElts + PartElts - 1) / PartElts);
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LLT RoundedDestTy = LLT::vector(RoundedElts, PartLLT.getElementType());
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auto RoundedConcat = MIRBuilder.buildConcatVectors(RoundedDestTy, Regs);
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MIRBuilder.buildExtract(OrigRegs[0], RoundedConcat, 0);
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auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs);
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B.buildExtract(OrigRegs[0], RoundedConcat, 0);
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}
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return;
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@@ -520,7 +520,7 @@ static void packSplitRegsToOrigType(MachineIRBuilder &MIRBuilder,
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LLT DstEltTy = LLTy.getElementType();
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if (DstEltTy == PartLLT) {
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// Vector was trivially scalarized.
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MIRBuilder.buildBuildVector(OrigRegs[0], Regs);
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B.buildBuildVector(OrigRegs[0], Regs);
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} else if (DstEltTy.getSizeInBits() > PartLLT.getSizeInBits()) {
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// Deal with vector with 64-bit elements decomposed to 32-bit
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// registers. Need to create intermediate 64-bit elements.
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@@ -530,23 +530,23 @@ static void packSplitRegsToOrigType(MachineIRBuilder &MIRBuilder,
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assert(DstEltTy.getSizeInBits() % PartLLT.getSizeInBits() == 0);
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for (int I = 0, NumElts = LLTy.getNumElements(); I != NumElts; ++I) {
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auto Merge = MIRBuilder.buildMerge(DstEltTy,
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auto Merge = B.buildMerge(DstEltTy,
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Regs.take_front(PartsPerElt));
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EltMerges.push_back(Merge.getReg(0));
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Regs = Regs.drop_front(PartsPerElt);
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}
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MIRBuilder.buildBuildVector(OrigRegs[0], EltMerges);
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B.buildBuildVector(OrigRegs[0], EltMerges);
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} else {
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// Vector was split, and elements promoted to a wider type.
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LLT BVType = LLT::vector(LLTy.getNumElements(), PartLLT);
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auto BV = MIRBuilder.buildBuildVector(BVType, Regs);
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MIRBuilder.buildTrunc(OrigRegs[0], BV);
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auto BV = B.buildBuildVector(BVType, Regs);
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B.buildTrunc(OrigRegs[0], BV);
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}
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}
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bool AMDGPUCallLowering::lowerFormalArguments(
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MachineIRBuilder &MIRBuilder, const Function &F,
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MachineIRBuilder &B, const Function &F,
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ArrayRef<ArrayRef<Register>> VRegs) const {
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CallingConv::ID CC = F.getCallingConv();
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@@ -554,13 +554,13 @@ bool AMDGPUCallLowering::lowerFormalArguments(
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// useless for kernels. We want to avoid any kind of legalization or argument
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// splitting.
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if (CC == CallingConv::AMDGPU_KERNEL)
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return lowerFormalArgumentsKernel(MIRBuilder, F, VRegs);
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return lowerFormalArgumentsKernel(B, F, VRegs);
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const bool IsShader = AMDGPU::isShader(CC);
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const bool IsEntryFunc = AMDGPU::isEntryFunctionCC(CC);
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MachineFunction &MF = MIRBuilder.getMF();
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MachineBasicBlock &MBB = MIRBuilder.getMBB();
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MachineFunction &MF = B.getMF();
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MachineBasicBlock &MBB = B.getMBB();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
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const GCNSubtarget &Subtarget = MF.getSubtarget<GCNSubtarget>();
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@@ -576,7 +576,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
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Register LiveInReturn = MF.addLiveIn(ReturnAddrReg,
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&AMDGPU::SGPR_64RegClass);
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MBB.addLiveIn(ReturnAddrReg);
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MIRBuilder.buildCopy(LiveInReturn, ReturnAddrReg);
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B.buildCopy(LiveInReturn, ReturnAddrReg);
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}
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if (Info->hasImplicitBufferPtr()) {
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@@ -619,7 +619,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
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if (SkipArg) {
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for (int I = 0, E = VRegs[Idx].size(); I != E; ++I)
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MIRBuilder.buildUndef(VRegs[Idx][I]);
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B.buildUndef(VRegs[Idx][I]);
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++Idx;
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continue;
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@@ -634,7 +634,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
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// FIXME: We should probably be passing multiple registers to
|
||||
// handleAssignments to do this
|
||||
[&](ArrayRef<Register> Regs, LLT LLTy, LLT PartLLT, int VTSplitIdx) {
|
||||
packSplitRegsToOrigType(MIRBuilder, VRegs[Idx][VTSplitIdx], Regs,
|
||||
packSplitRegsToOrigType(B, VRegs[Idx][VTSplitIdx], Regs,
|
||||
LLTy, PartLLT);
|
||||
});
|
||||
|
||||
@@ -686,10 +686,10 @@ bool AMDGPUCallLowering::lowerFormalArguments(
|
||||
CCAssignFn *AssignFn = TLI.CCAssignFnForCall(CC, F.isVarArg());
|
||||
|
||||
if (!MBB.empty())
|
||||
MIRBuilder.setInstr(*MBB.begin());
|
||||
B.setInstr(*MBB.begin());
|
||||
|
||||
FormalArgHandler Handler(MIRBuilder, MRI, AssignFn);
|
||||
if (!handleAssignments(CCInfo, ArgLocs, MIRBuilder, SplitArgs, Handler))
|
||||
FormalArgHandler Handler(B, MRI, AssignFn);
|
||||
if (!handleAssignments(CCInfo, ArgLocs, B, SplitArgs, Handler))
|
||||
return false;
|
||||
|
||||
if (!IsEntryFunc) {
|
||||
@@ -708,7 +708,7 @@ bool AMDGPUCallLowering::lowerFormalArguments(
|
||||
}
|
||||
|
||||
// Move back to the end of the basic block.
|
||||
MIRBuilder.setMBB(MBB);
|
||||
B.setMBB(MBB);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -23,12 +23,11 @@ class AMDGPUTargetLowering;
|
||||
class MachineInstrBuilder;
|
||||
|
||||
class AMDGPUCallLowering: public CallLowering {
|
||||
Register lowerParameterPtr(MachineIRBuilder &MIRBuilder, Type *ParamTy,
|
||||
Register lowerParameterPtr(MachineIRBuilder &B, Type *ParamTy,
|
||||
uint64_t Offset) const;
|
||||
|
||||
void lowerParameter(MachineIRBuilder &MIRBuilder, Type *ParamTy,
|
||||
uint64_t Offset, unsigned Align,
|
||||
Register DstReg) const;
|
||||
void lowerParameter(MachineIRBuilder &B, Type *ParamTy, uint64_t Offset,
|
||||
unsigned Align, Register DstReg) const;
|
||||
|
||||
/// A function of this type is used to perform value split action.
|
||||
using SplitArgTy = std::function<void(ArrayRef<Register>, LLT, LLT, int)>;
|
||||
@@ -39,21 +38,19 @@ class AMDGPUCallLowering: public CallLowering {
|
||||
CallingConv::ID CallConv,
|
||||
SplitArgTy SplitArg) const;
|
||||
|
||||
bool lowerReturnVal(MachineIRBuilder &MIRBuilder,
|
||||
const Value *Val, ArrayRef<Register> VRegs,
|
||||
MachineInstrBuilder &Ret) const;
|
||||
bool lowerReturnVal(MachineIRBuilder &B, const Value *Val,
|
||||
ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
|
||||
|
||||
public:
|
||||
AMDGPUCallLowering(const AMDGPUTargetLowering &TLI);
|
||||
|
||||
bool lowerReturn(MachineIRBuilder &MIRBuilder, const Value *Val,
|
||||
bool lowerReturn(MachineIRBuilder &B, const Value *Val,
|
||||
ArrayRef<Register> VRegs) const override;
|
||||
|
||||
bool lowerFormalArgumentsKernel(MachineIRBuilder &MIRBuilder,
|
||||
const Function &F,
|
||||
bool lowerFormalArgumentsKernel(MachineIRBuilder &B, const Function &F,
|
||||
ArrayRef<ArrayRef<Register>> VRegs) const;
|
||||
|
||||
bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
|
||||
bool lowerFormalArguments(MachineIRBuilder &B, const Function &F,
|
||||
ArrayRef<ArrayRef<Register>> VRegs) const override;
|
||||
static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
|
||||
static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
|
||||
|
||||
@@ -823,35 +823,35 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
|
||||
|
||||
bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
|
||||
MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder,
|
||||
MachineIRBuilder &B,
|
||||
GISelChangeObserver &Observer) const {
|
||||
switch (MI.getOpcode()) {
|
||||
case TargetOpcode::G_ADDRSPACE_CAST:
|
||||
return legalizeAddrSpaceCast(MI, MRI, MIRBuilder);
|
||||
return legalizeAddrSpaceCast(MI, MRI, B);
|
||||
case TargetOpcode::G_FRINT:
|
||||
return legalizeFrint(MI, MRI, MIRBuilder);
|
||||
return legalizeFrint(MI, MRI, B);
|
||||
case TargetOpcode::G_FCEIL:
|
||||
return legalizeFceil(MI, MRI, MIRBuilder);
|
||||
return legalizeFceil(MI, MRI, B);
|
||||
case TargetOpcode::G_INTRINSIC_TRUNC:
|
||||
return legalizeIntrinsicTrunc(MI, MRI, MIRBuilder);
|
||||
return legalizeIntrinsicTrunc(MI, MRI, B);
|
||||
case TargetOpcode::G_SITOFP:
|
||||
return legalizeITOFP(MI, MRI, MIRBuilder, true);
|
||||
return legalizeITOFP(MI, MRI, B, true);
|
||||
case TargetOpcode::G_UITOFP:
|
||||
return legalizeITOFP(MI, MRI, MIRBuilder, false);
|
||||
return legalizeITOFP(MI, MRI, B, false);
|
||||
case TargetOpcode::G_FMINNUM:
|
||||
case TargetOpcode::G_FMAXNUM:
|
||||
case TargetOpcode::G_FMINNUM_IEEE:
|
||||
case TargetOpcode::G_FMAXNUM_IEEE:
|
||||
return legalizeMinNumMaxNum(MI, MRI, MIRBuilder);
|
||||
return legalizeMinNumMaxNum(MI, MRI, B);
|
||||
case TargetOpcode::G_EXTRACT_VECTOR_ELT:
|
||||
return legalizeExtractVectorElt(MI, MRI, MIRBuilder);
|
||||
return legalizeExtractVectorElt(MI, MRI, B);
|
||||
case TargetOpcode::G_INSERT_VECTOR_ELT:
|
||||
return legalizeInsertVectorElt(MI, MRI, MIRBuilder);
|
||||
return legalizeInsertVectorElt(MI, MRI, B);
|
||||
case TargetOpcode::G_FSIN:
|
||||
case TargetOpcode::G_FCOS:
|
||||
return legalizeSinCos(MI, MRI, MIRBuilder);
|
||||
return legalizeSinCos(MI, MRI, B);
|
||||
case TargetOpcode::G_GLOBAL_VALUE:
|
||||
return legalizeGlobalValue(MI, MRI, MIRBuilder);
|
||||
return legalizeGlobalValue(MI, MRI, B);
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
@@ -862,8 +862,8 @@ bool AMDGPULegalizerInfo::legalizeCustom(MachineInstr &MI,
|
||||
Register AMDGPULegalizerInfo::getSegmentAperture(
|
||||
unsigned AS,
|
||||
MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const {
|
||||
MachineFunction &MF = MIRBuilder.getMF();
|
||||
MachineIRBuilder &B) const {
|
||||
MachineFunction &MF = B.getMF();
|
||||
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
|
||||
@@ -884,13 +884,13 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
|
||||
Register ApertureReg = MRI.createGenericVirtualRegister(S32);
|
||||
Register GetReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
|
||||
|
||||
MIRBuilder.buildInstr(AMDGPU::S_GETREG_B32)
|
||||
B.buildInstr(AMDGPU::S_GETREG_B32)
|
||||
.addDef(GetReg)
|
||||
.addImm(Encoding);
|
||||
MRI.setType(GetReg, S32);
|
||||
|
||||
auto ShiftAmt = MIRBuilder.buildConstant(S32, WidthM1 + 1);
|
||||
MIRBuilder.buildInstr(TargetOpcode::G_SHL)
|
||||
auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1);
|
||||
B.buildInstr(TargetOpcode::G_SHL)
|
||||
.addDef(ApertureReg)
|
||||
.addUse(GetReg)
|
||||
.addUse(ShiftAmt.getReg(0));
|
||||
@@ -902,7 +902,7 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
|
||||
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64));
|
||||
|
||||
const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
|
||||
if (!loadInputValue(QueuePtr, MIRBuilder, &MFI->getArgInfo().QueuePtr))
|
||||
if (!loadInputValue(QueuePtr, B, &MFI->getArgInfo().QueuePtr))
|
||||
return Register();
|
||||
|
||||
// Offset into amd_queue_t for group_segment_aperture_base_hi /
|
||||
@@ -926,17 +926,17 @@ Register AMDGPULegalizerInfo::getSegmentAperture(
|
||||
Register LoadResult = MRI.createGenericVirtualRegister(S32);
|
||||
Register LoadAddr;
|
||||
|
||||
MIRBuilder.materializeGEP(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
|
||||
MIRBuilder.buildLoad(LoadResult, LoadAddr, *MMO);
|
||||
B.materializeGEP(LoadAddr, QueuePtr, LLT::scalar(64), StructOffset);
|
||||
B.buildLoad(LoadResult, LoadAddr, *MMO);
|
||||
return LoadResult;
|
||||
}
|
||||
|
||||
bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
||||
MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const {
|
||||
MachineFunction &MF = MIRBuilder.getMF();
|
||||
MachineIRBuilder &B) const {
|
||||
MachineFunction &MF = B.getMF();
|
||||
|
||||
MIRBuilder.setInstr(MI);
|
||||
B.setInstr(MI);
|
||||
|
||||
const LLT S32 = LLT::scalar(32);
|
||||
Register Dst = MI.getOperand(0).getReg();
|
||||
@@ -956,13 +956,13 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
||||
|
||||
const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
|
||||
if (ST.getTargetLowering()->isNoopAddrSpaceCast(SrcAS, DestAS)) {
|
||||
MI.setDesc(MIRBuilder.getTII().get(TargetOpcode::G_BITCAST));
|
||||
MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST));
|
||||
return true;
|
||||
}
|
||||
|
||||
if (DestAS == AMDGPUAS::CONSTANT_ADDRESS_32BIT) {
|
||||
// Truncate.
|
||||
MIRBuilder.buildExtract(Dst, Src, 0);
|
||||
B.buildExtract(Dst, Src, 0);
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
@@ -974,9 +974,9 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
||||
// FIXME: This is a bit ugly due to creating a merge of 2 pointers to
|
||||
// another. Merge operands are required to be the same type, but creating an
|
||||
// extra ptrtoint would be kind of pointless.
|
||||
auto HighAddr = MIRBuilder.buildConstant(
|
||||
auto HighAddr = B.buildConstant(
|
||||
LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS_32BIT, 32), AddrHiVal);
|
||||
MIRBuilder.buildMerge(Dst, {Src, HighAddr.getReg(0)});
|
||||
B.buildMerge(Dst, {Src, HighAddr.getReg(0)});
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
}
|
||||
@@ -986,17 +986,17 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
||||
DestAS == AMDGPUAS::PRIVATE_ADDRESS);
|
||||
unsigned NullVal = TM.getNullPointerValue(DestAS);
|
||||
|
||||
auto SegmentNull = MIRBuilder.buildConstant(DstTy, NullVal);
|
||||
auto FlatNull = MIRBuilder.buildConstant(SrcTy, 0);
|
||||
auto SegmentNull = B.buildConstant(DstTy, NullVal);
|
||||
auto FlatNull = B.buildConstant(SrcTy, 0);
|
||||
|
||||
Register PtrLo32 = MRI.createGenericVirtualRegister(DstTy);
|
||||
|
||||
// Extract low 32-bits of the pointer.
|
||||
MIRBuilder.buildExtract(PtrLo32, Src, 0);
|
||||
B.buildExtract(PtrLo32, Src, 0);
|
||||
|
||||
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
|
||||
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
|
||||
MIRBuilder.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
|
||||
B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, FlatNull.getReg(0));
|
||||
B.buildSelect(Dst, CmpRes, PtrLo32, SegmentNull.getReg(0));
|
||||
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
@@ -1009,29 +1009,29 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
||||
return false;
|
||||
|
||||
auto SegmentNull =
|
||||
MIRBuilder.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
|
||||
B.buildConstant(SrcTy, TM.getNullPointerValue(SrcAS));
|
||||
auto FlatNull =
|
||||
MIRBuilder.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
|
||||
B.buildConstant(DstTy, TM.getNullPointerValue(DestAS));
|
||||
|
||||
Register ApertureReg = getSegmentAperture(DestAS, MRI, MIRBuilder);
|
||||
Register ApertureReg = getSegmentAperture(DestAS, MRI, B);
|
||||
if (!ApertureReg.isValid())
|
||||
return false;
|
||||
|
||||
Register CmpRes = MRI.createGenericVirtualRegister(LLT::scalar(1));
|
||||
MIRBuilder.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
|
||||
B.buildICmp(CmpInst::ICMP_NE, CmpRes, Src, SegmentNull.getReg(0));
|
||||
|
||||
Register BuildPtr = MRI.createGenericVirtualRegister(DstTy);
|
||||
|
||||
// Coerce the type of the low half of the result so we can use merge_values.
|
||||
Register SrcAsInt = MRI.createGenericVirtualRegister(S32);
|
||||
MIRBuilder.buildInstr(TargetOpcode::G_PTRTOINT)
|
||||
B.buildInstr(TargetOpcode::G_PTRTOINT)
|
||||
.addDef(SrcAsInt)
|
||||
.addUse(Src);
|
||||
|
||||
// TODO: Should we allow mismatched types but matching sizes in merges to
|
||||
// avoid the ptrtoint?
|
||||
MIRBuilder.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
|
||||
MIRBuilder.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
|
||||
B.buildMerge(BuildPtr, {SrcAsInt, ApertureReg});
|
||||
B.buildSelect(Dst, CmpRes, BuildPtr, FlatNull.getReg(0));
|
||||
|
||||
MI.eraseFromParent();
|
||||
return true;
|
||||
@@ -1039,8 +1039,8 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
|
||||
|
||||
bool AMDGPULegalizerInfo::legalizeFrint(
|
||||
MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const {
|
||||
MIRBuilder.setInstr(MI);
|
||||
MachineIRBuilder &B) const {
|
||||
B.setInstr(MI);
|
||||
|
||||
Register Src = MI.getOperand(1).getReg();
|
||||
LLT Ty = MRI.getType(Src);
|
||||
@@ -1049,18 +1049,18 @@ bool AMDGPULegalizerInfo::legalizeFrint(
|
||||
APFloat C1Val(APFloat::IEEEdouble(), "0x1.0p+52");
|
||||
APFloat C2Val(APFloat::IEEEdouble(), "0x1.fffffffffffffp+51");
|
||||
|
||||
auto C1 = MIRBuilder.buildFConstant(Ty, C1Val);
|
||||
auto CopySign = MIRBuilder.buildFCopysign(Ty, C1, Src);
|
||||
auto C1 = B.buildFConstant(Ty, C1Val);
|
||||
auto CopySign = B.buildFCopysign(Ty, C1, Src);
|
||||
|
||||
// TODO: Should this propagate fast-math-flags?
|
||||
auto Tmp1 = MIRBuilder.buildFAdd(Ty, Src, CopySign);
|
||||
auto Tmp2 = MIRBuilder.buildFSub(Ty, Tmp1, CopySign);
|
||||
auto Tmp1 = B.buildFAdd(Ty, Src, CopySign);
|
||||
auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign);
|
||||
|
||||
auto C2 = MIRBuilder.buildFConstant(Ty, C2Val);
|
||||
auto Fabs = MIRBuilder.buildFAbs(Ty, Src);
|
||||
auto C2 = B.buildFConstant(Ty, C2Val);
|
||||
auto Fabs = B.buildFAbs(Ty, Src);
|
||||
|
||||
auto Cond = MIRBuilder.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
|
||||
MIRBuilder.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
|
||||
auto Cond = B.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
|
||||
B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -32,34 +32,34 @@ public:
|
||||
const GCNTargetMachine &TM);
|
||||
|
||||
bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder,
|
||||
MachineIRBuilder &B,
|
||||
GISelChangeObserver &Observer) const override;
|
||||
|
||||
Register getSegmentAperture(unsigned AddrSpace,
|
||||
MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
|
||||
bool legalizeAddrSpaceCast(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeFrint(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeFceil(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeIntrinsicTrunc(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeITOFP(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder, bool Signed) const;
|
||||
MachineIRBuilder &B, bool Signed) const;
|
||||
bool legalizeMinNumMaxNum(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeExtractVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeInsertVectorElt(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
bool legalizeSinCos(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
|
||||
bool legalizeGlobalValue(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const;
|
||||
MachineIRBuilder &B) const;
|
||||
|
||||
Register getLiveInRegister(MachineRegisterInfo &MRI,
|
||||
Register Reg, LLT Ty) const;
|
||||
@@ -78,7 +78,7 @@ public:
|
||||
bool legalizeIsAddrSpace(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &B, unsigned AddrSpace) const;
|
||||
bool legalizeIntrinsic(MachineInstr &MI, MachineRegisterInfo &MRI,
|
||||
MachineIRBuilder &MIRBuilder) const override;
|
||||
MachineIRBuilder &B) const override;
|
||||
|
||||
};
|
||||
} // End llvm namespace.
|
||||
|
||||
Reference in New Issue
Block a user