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Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake
Summary: 1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake; 2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision. VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data. VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data. VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision. For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference Author: LiuTianle Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel Reviewed By: craig.topper Subscribers: kristina, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60550 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360017 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Luo, Yuanke
@@ -4834,3 +4834,41 @@ let TargetPrefix = "x86" in {
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def int_x86_invpcid : GCCBuiltin<"__builtin_ia32_invpcid">,
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Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], []>;
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}
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let TargetPrefix = "x86" in {
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def int_x86_avx512bf16_cvtne2ps2bf16_128:
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GCCBuiltin<"__builtin_ia32_cvtne2ps2bf16_128">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v4f32_ty, llvm_v4f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512bf16_cvtne2ps2bf16_256:
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GCCBuiltin<"__builtin_ia32_cvtne2ps2bf16_256">,
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Intrinsic<[llvm_v16i16_ty], [llvm_v8f32_ty, llvm_v8f32_ty],
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[IntrNoMem]>;
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def int_x86_avx512bf16_cvtne2ps2bf16_512:
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GCCBuiltin<"__builtin_ia32_cvtne2ps2bf16_512">,
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Intrinsic<[llvm_v32i16_ty], [llvm_v16f32_ty, llvm_v16f32_ty],
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[IntrNoMem]>;
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// Intrinsic must be masked due to it producing less than 128 bits of results.
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def int_x86_avx512bf16_mask_cvtneps2bf16_128:
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v4f32_ty, llvm_v8i16_ty, llvm_v4i1_ty],
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[IntrNoMem]>;
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def int_x86_avx512bf16_cvtneps2bf16_256:
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GCCBuiltin<"__builtin_ia32_cvtneps2bf16_256">,
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Intrinsic<[llvm_v8i16_ty], [llvm_v8f32_ty], [IntrNoMem]>;
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def int_x86_avx512bf16_cvtneps2bf16_512:
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GCCBuiltin<"__builtin_ia32_cvtneps2bf16_512">,
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Intrinsic<[llvm_v16i16_ty], [llvm_v16f32_ty], [IntrNoMem]>;
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def int_x86_avx512bf16_dpbf16ps_128:
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GCCBuiltin<"__builtin_ia32_dpbf16ps_128">,
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Intrinsic<[llvm_v4f32_ty],
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[llvm_v4f32_ty, llvm_v4i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
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def int_x86_avx512bf16_dpbf16ps_256:
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GCCBuiltin<"__builtin_ia32_dpbf16ps_256">,
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Intrinsic<[llvm_v8f32_ty],
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[llvm_v8f32_ty, llvm_v8i32_ty, llvm_v8i32_ty], [IntrNoMem]>;
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def int_x86_avx512bf16_dpbf16ps_512:
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GCCBuiltin<"__builtin_ia32_dpbf16ps_512">,
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Intrinsic<[llvm_v16f32_ty],
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[llvm_v16f32_ty, llvm_v16i32_ty, llvm_v16i32_ty], [IntrNoMem]>;
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}
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@@ -1375,6 +1375,9 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
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// detecting features using the "-march=native" flag.
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// For more info, see X86 ISA docs.
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Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
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bool HasLeaf7Subleaf1 =
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MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x1, &EAX, &EBX, &ECX, &EDX);
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Features["avx512bf16"] = HasLeaf7Subleaf1 && ((EAX >> 5) & 1) && HasAVX512Save;
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bool HasLeafD = MaxLevel >= 0xd &&
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!getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
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@@ -167,6 +167,9 @@ def FeaturePKU : SubtargetFeature<"pku", "HasPKU", "true",
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def FeatureVNNI : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
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"Enable AVX-512 Vector Neural Network Instructions",
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[FeatureAVX512]>;
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def FeatureBF16 : SubtargetFeature<"avx512bf16", "HasBF16", "true",
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"Support bfloat16 floating point",
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[FeatureBWI]>;
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def FeatureBITALG : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
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"Enable AVX-512 Bit Algorithms",
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[FeatureBWI]>;
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@@ -22624,6 +22624,21 @@ SDValue X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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PassThru, Mask);
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}
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case CVTNEPS2BF16_MASK: {
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SDValue Src = Op.getOperand(1);
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SDValue PassThru = Op.getOperand(2);
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SDValue Mask = Op.getOperand(3);
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if (ISD::isBuildVectorAllOnes(Mask.getNode()))
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Src);
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// Break false dependency.
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if (PassThru.isUndef())
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PassThru = DAG.getConstant(0, dl, PassThru.getValueType());
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return DAG.getNode(IntrData->Opc1, dl, Op.getValueType(), Src, PassThru,
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Mask);
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}
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default:
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break;
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}
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@@ -28073,6 +28088,10 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const {
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case X86ISD::CVTS2UI: return "X86ISD::CVTS2UI";
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case X86ISD::CVTS2SI_RND: return "X86ISD::CVTS2SI_RND";
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case X86ISD::CVTS2UI_RND: return "X86ISD::CVTS2UI_RND";
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case X86ISD::CVTNE2PS2BF16: return "X86ISD::CVTNE2PS2BF16";
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case X86ISD::CVTNEPS2BF16: return "X86ISD::CVTNEPS2BF16";
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case X86ISD::MCVTNEPS2BF16: return "X86ISD::MCVTNEPS2BF16";
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case X86ISD::DPBF16PS: return "X86ISD::DPBF16PS";
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case X86ISD::LWPINS: return "X86ISD::LWPINS";
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case X86ISD::MGATHER: return "X86ISD::MGATHER";
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case X86ISD::MSCATTER: return "X86ISD::MSCATTER";
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@@ -509,6 +509,19 @@ namespace llvm {
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MCVTP2SI, MCVTP2UI, MCVTTP2SI, MCVTTP2UI,
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MCVTSI2P, MCVTUI2P,
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// Vector float to bfloat16.
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// Convert TWO packed single data to one packed BF16 data
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CVTNE2PS2BF16,
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// Convert packed single data to packed BF16 data
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CVTNEPS2BF16,
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// Masked version of above.
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// SRC, PASSTHRU, MASK
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MCVTNEPS2BF16,
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// Dot product of BF16 pairs to accumulated into
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// packed single precision.
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DPBF16PS,
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// Save xmm argument registers to the stack, according to %al. An operator
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// is needed so that this can be expanded with control flow.
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VASTART_SAVE_XMM_REGS,
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@@ -12647,3 +12647,143 @@ defm VP4DPWSSDSrm : AVX512_maskable_3src_in_asm<0x53, MRMSrcMem, v16i32_info,
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Sched<[SchedWriteFMA.ZMM.Folded]>;
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}
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multiclass avx512_binop_all2<bits<8> opc, string OpcodeStr,
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X86SchedWriteWidths sched,
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AVX512VLVectorVTInfo _SrcVTInfo,
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AVX512VLVectorVTInfo _DstVTInfo,
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SDNode OpNode, Predicate prd,
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bit IsCommutable = 0> {
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let Predicates = [prd] in
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defm NAME#Z : avx512_binop_rm2<opc, OpcodeStr, sched.ZMM, OpNode,
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_SrcVTInfo.info512, _DstVTInfo.info512,
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_SrcVTInfo.info512, IsCommutable>,
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EVEX_V512, EVEX_CD8<32, CD8VF>;
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let Predicates = [HasVLX, prd] in {
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defm NAME#Z256 : avx512_binop_rm2<opc, OpcodeStr, sched.YMM, OpNode,
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_SrcVTInfo.info256, _DstVTInfo.info256,
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_SrcVTInfo.info256, IsCommutable>,
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EVEX_V256, EVEX_CD8<32, CD8VF>;
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defm NAME#Z128 : avx512_binop_rm2<opc, OpcodeStr, sched.XMM, OpNode,
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_SrcVTInfo.info128, _DstVTInfo.info128,
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_SrcVTInfo.info128, IsCommutable>,
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EVEX_V128, EVEX_CD8<32, CD8VF>;
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}
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}
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defm VCVTNE2PS2BF16 : avx512_binop_all2<0x72, "vcvtne2ps2bf16",
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SchedWriteCvtPD2PS, //FIXME: Shoulod be SchedWriteCvtPS2BF
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avx512vl_f32_info, avx512vl_i16_info,
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X86cvtne2ps2bf16, HasBF16, 0>, T8XD;
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// Truncate Float to BFloat16
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multiclass avx512_cvtps2bf16<bits<8> opc, string OpcodeStr,
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X86SchedWriteWidths sched> {
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let Predicates = [HasBF16] in {
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defm Z : avx512_vcvt_fp<opc, OpcodeStr, v16i16x_info, v16f32_info,
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X86cvtneps2bf16, sched.ZMM>, EVEX_V512;
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}
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let Predicates = [HasBF16, HasVLX] in {
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defm Z128 : avx512_vcvt_fp<opc, OpcodeStr, v8i16x_info, v4f32x_info,
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null_frag, sched.XMM, "{1to4}", "{x}", f128mem,
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VK4WM>, EVEX_V128;
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defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v8i16x_info, v8f32x_info,
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X86cvtneps2bf16,
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sched.YMM, "{1to8}", "{y}">, EVEX_V256;
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def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "Z128rr") VR128X:$dst,
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VR128X:$src), 0>;
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def : InstAlias<OpcodeStr##"x\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "Z128rm") VR128X:$dst,
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f128mem:$src), 0, "intel">;
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def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "Z256rr") VR128X:$dst,
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VR256X:$src), 0>;
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def : InstAlias<OpcodeStr##"y\t{$src, $dst|$dst, $src}",
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(!cast<Instruction>(NAME # "Z256rm") VR128X:$dst,
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f256mem:$src), 0, "intel">;
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}
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}
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defm VCVTNEPS2BF16 : avx512_cvtps2bf16<0x72, "vcvtneps2bf16",
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SchedWriteCvtPD2PS>, T8XS,
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EVEX_CD8<32, CD8VF>;
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let Predicates = [HasBF16, HasVLX] in {
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// Special patterns to allow use of X86mcvtneps2bf16 for masking. Instruction
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// patterns have been disabled with null_frag.
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def : Pat<(v8i16 (X86cvtneps2bf16 (v4f32 VR128X:$src))),
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(VCVTNEPS2BF16Z128rr VR128X:$src)>;
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def : Pat<(X86mcvtneps2bf16 (v4f32 VR128X:$src), (v8i16 VR128X:$src0),
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VK4WM:$mask),
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(VCVTNEPS2BF16Z128rrk VR128X:$src0, VK4WM:$mask, VR128X:$src)>;
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def : Pat<(X86mcvtneps2bf16 (v4f32 VR128X:$src), v8i16x_info.ImmAllZerosV,
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VK4WM:$mask),
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(VCVTNEPS2BF16Z128rrkz VK4WM:$mask, VR128X:$src)>;
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def : Pat<(v8i16 (X86cvtneps2bf16 (loadv4f32 addr:$src))),
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(VCVTNEPS2BF16Z128rm addr:$src)>;
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def : Pat<(X86mcvtneps2bf16 (loadv4f32 addr:$src), (v8i16 VR128X:$src0),
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VK4WM:$mask),
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(VCVTNEPS2BF16Z128rmk VR128X:$src0, VK4WM:$mask, addr:$src)>;
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def : Pat<(X86mcvtneps2bf16 (loadv4f32 addr:$src), v8i16x_info.ImmAllZerosV,
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VK4WM:$mask),
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(VCVTNEPS2BF16Z128rmkz VK4WM:$mask, addr:$src)>;
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def : Pat<(v8i16 (X86cvtneps2bf16 (v4f32
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(X86VBroadcast (loadf32 addr:$src))))),
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(VCVTNEPS2BF16Z128rmb addr:$src)>;
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def : Pat<(X86mcvtneps2bf16 (v4f32 (X86VBroadcast (loadf32 addr:$src))),
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(v8i16 VR128X:$src0), VK4WM:$mask),
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(VCVTNEPS2BF16Z128rmbk VR128X:$src0, VK4WM:$mask, addr:$src)>;
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def : Pat<(X86mcvtneps2bf16 (v4f32 (X86VBroadcast (loadf32 addr:$src))),
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v8i16x_info.ImmAllZerosV, VK4WM:$mask),
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(VCVTNEPS2BF16Z128rmbkz VK4WM:$mask, addr:$src)>;
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}
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let Constraints = "$src1 = $dst" in {
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multiclass avx512_dpbf16ps_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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X86VectorVTInfo _, X86VectorVTInfo src_v> {
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defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.RC:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
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EVEX_4V;
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defm m: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.MemOp:$src3),
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OpcodeStr, "$src3, $src2", "$src2, $src3",
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(_.VT (OpNode _.RC:$src1, _.RC:$src2,
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(src_v.VT (bitconvert
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(src_v.LdFrag addr:$src3)))))>, EVEX_4V;
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defm mb: AVX512_maskable_3src<opc, MRMSrcMem, _, (outs _.RC:$dst),
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(ins _.RC:$src2, _.ScalarMemOp:$src3),
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OpcodeStr,
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!strconcat("${src3}", _.BroadcastStr,", $src2"),
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!strconcat("$src2, ${src3}", _.BroadcastStr),
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(_.VT (OpNode _.RC:$src1, _.RC:$src2,
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(src_v.VT (X86VBroadcast(src_v.ScalarLdFrag addr:$src3)))))>,
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EVEX_B, EVEX_4V;
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}
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} // Constraints = "$src1 = $dst"
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multiclass avx512_dpbf16ps_sizes<bits<8> opc, string OpcodeStr, SDNode OpNode,
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AVX512VLVectorVTInfo _,
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AVX512VLVectorVTInfo src_v, Predicate prd> {
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let Predicates = [prd] in {
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defm Z : avx512_dpbf16ps_rm<opc, OpcodeStr, OpNode, _.info512,
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src_v.info512>, EVEX_V512;
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}
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let Predicates = [HasVLX, prd] in {
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defm Z256 : avx512_dpbf16ps_rm<opc, OpcodeStr, OpNode, _.info256,
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src_v.info256>, EVEX_V256;
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defm Z128 : avx512_dpbf16ps_rm<opc, OpcodeStr, OpNode, _.info128,
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src_v.info128>, EVEX_V128;
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}
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}
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defm VDPBF16PS : avx512_dpbf16ps_sizes<0x52, "vdpbf16ps", X86dpbf16ps,
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avx512vl_f32_info, avx512vl_i32_info,
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HasBF16>, T8XS, EVEX_CD8<32, CD8VF>;
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@@ -664,6 +664,25 @@ def X86vfproundRnd: SDNode<"X86ISD::VFPROUND_RND",
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SDTCisOpSmallerThanOp<0, 1>,
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SDTCisVT<2, i32>]>>;
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// cvt fp to bfloat16
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def X86cvtne2ps2bf16 : SDNode<"X86ISD::CVTNE2PS2BF16",
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SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
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SDTCisSameAs<1,2>]>>;
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def X86mcvtneps2bf16 : SDNode<"X86ISD::MCVTNEPS2BF16",
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, i16>,
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SDTCVecEltisVT<1, f32>,
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SDTCisSameAs<0, 2>,
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SDTCVecEltisVT<3, i1>,
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SDTCisSameNumEltsAs<1, 3>]>>;
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def X86cvtneps2bf16 : SDNode<"X86ISD::CVTNEPS2BF16",
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SDTypeProfile<1, 1, [SDTCVecEltisVT<0, i16>,
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SDTCVecEltisVT<1, f32>]>>;
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def X86dpbf16ps : SDNode<"X86ISD::DPBF16PS",
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SDTypeProfile<1, 3, [SDTCVecEltisVT<0, f32>,
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SDTCisSameAs<0,1>,
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SDTCVecEltisVT<2, i32>,
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SDTCisSameAs<2,3>]>>;
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// galois field arithmetic
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def X86GF2P8affineinvqb : SDNode<"X86ISD::GF2P8AFFINEINVQB", SDTBlend>;
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def X86GF2P8affineqb : SDNode<"X86ISD::GF2P8AFFINEQB", SDTBlend>;
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@@ -835,6 +835,7 @@ def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">;
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def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">;
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def PKU : Predicate<"Subtarget->hasPKU()">;
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def HasVNNI : Predicate<"Subtarget->hasVNNI()">;
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def HasBF16 : Predicate<"Subtarget->hasBF16()">;
|
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def HasBITALG : Predicate<"Subtarget->hasBITALG()">;
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def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">;
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@@ -19,6 +19,7 @@
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namespace llvm {
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enum IntrinsicType : uint16_t {
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CVTNEPS2BF16_MASK,
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GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST, XGETBV, ADX, FPCLASSS,
|
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INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP, INTR_TYPE_4OP,
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INTR_TYPE_3OP_IMM8,
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@@ -981,6 +982,16 @@ static const IntrinsicData IntrinsicsWithoutChain[] = {
|
||||
X86_INTRINSIC_DATA(avx512_vpshufbitqmb_128, INTR_TYPE_2OP, X86ISD::VPSHUFBITQMB, 0),
|
||||
X86_INTRINSIC_DATA(avx512_vpshufbitqmb_256, INTR_TYPE_2OP, X86ISD::VPSHUFBITQMB, 0),
|
||||
X86_INTRINSIC_DATA(avx512_vpshufbitqmb_512, INTR_TYPE_2OP, X86ISD::VPSHUFBITQMB, 0),
|
||||
// bfloat16
|
||||
X86_INTRINSIC_DATA(avx512bf16_cvtne2ps2bf16_128, INTR_TYPE_2OP, X86ISD::CVTNE2PS2BF16, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_cvtne2ps2bf16_256, INTR_TYPE_2OP, X86ISD::CVTNE2PS2BF16, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_cvtne2ps2bf16_512, INTR_TYPE_2OP, X86ISD::CVTNE2PS2BF16, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_cvtneps2bf16_256, INTR_TYPE_1OP, X86ISD::CVTNEPS2BF16, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_cvtneps2bf16_512, INTR_TYPE_1OP, X86ISD::CVTNEPS2BF16, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_dpbf16ps_128, INTR_TYPE_3OP, X86ISD::DPBF16PS, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_dpbf16ps_256, INTR_TYPE_3OP, X86ISD::DPBF16PS, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_dpbf16ps_512, INTR_TYPE_3OP, X86ISD::DPBF16PS, 0),
|
||||
X86_INTRINSIC_DATA(avx512bf16_mask_cvtneps2bf16_128, CVTNEPS2BF16_MASK, X86ISD::CVTNEPS2BF16, X86ISD::MCVTNEPS2BF16),
|
||||
X86_INTRINSIC_DATA(bmi_bextr_32, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
|
||||
X86_INTRINSIC_DATA(bmi_bextr_64, INTR_TYPE_2OP, X86ISD::BEXTR, 0),
|
||||
X86_INTRINSIC_DATA(bmi_bzhi_32, INTR_TYPE_2OP, X86ISD::BZHI, 0),
|
||||
|
||||
@@ -353,6 +353,9 @@ protected:
|
||||
/// Processor has AVX-512 Vector Neural Network Instructions
|
||||
bool HasVNNI = false;
|
||||
|
||||
/// Processor has AVX-512 bfloat16 floating-point extensions
|
||||
bool HasBF16 = false;
|
||||
|
||||
/// Processor has AVX-512 Bit Algorithms instructions
|
||||
bool HasBITALG = false;
|
||||
|
||||
@@ -668,6 +671,7 @@ public:
|
||||
bool hasVLX() const { return HasVLX; }
|
||||
bool hasPKU() const { return HasPKU; }
|
||||
bool hasVNNI() const { return HasVNNI; }
|
||||
bool hasBF16() const { return HasBF16; }
|
||||
bool hasBITALG() const { return HasBITALG; }
|
||||
bool hasMPX() const { return HasMPX; }
|
||||
bool hasSHSTK() const { return HasSHSTK; }
|
||||
|
||||
Reference in New Issue
Block a user