RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2026-07-19 15:13:49 -04:00
Code Issues Packages Projects Releases 10 Wiki Activity

[AMDGPU] Change register type for v32 vectors

Browse Source 
When it is AReg_1024 this results in unnecessary copying into
AGPRs of a 32 element vectors even though they are not intended
for an mfma instruction.

Differential Revision: https://reviews.llvm.org/D64815

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366252 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stanislav Mekhanoshin
2019-07-16 20:06:00 +00:00
parent f8b274f2cb
commit 10f786ca0f
2 changed files with 31 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/AMDGPU/SIISelLowering.cpp
+2 -2
View File
@@ -152,8 +152,8 @@ SITargetLowering::SITargetLowering(const TargetMachine &TM,
}
if (Subtarget->hasMAIInsts()) {
addRegisterClass(MVT::v32i32, &AMDGPU::AReg_1024RegClass);
addRegisterClass(MVT::v32f32, &AMDGPU::AReg_1024RegClass);
addRegisterClass(MVT::v32i32, &AMDGPU::VReg_1024RegClass);
addRegisterClass(MVT::v32f32, &AMDGPU::VReg_1024RegClass);
}
computeRegisterProperties(Subtarget->getRegisterInfo());
test/CodeGen/AMDGPU/v1024.ll
+29
View File
@@ -0,0 +1,29 @@
; RUN: llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Check that we do not use AGPRs for v32i32 type
; GCN-LABEL: {{^}}test_v1024:
; GCN-NOT: v_accvgpr
; GCN-COUNT-32: v_mov_b32_e32
; GCN-NOT: v_accvgpr
define amdgpu_kernel void @test_v1024() {
entry:
%alloca = alloca <32 x i32>, align 16, addrspace(5)
%cast = bitcast <32 x i32> addrspace(5)* %alloca to i8 addrspace(5)*
br i1 undef, label %if.then.i.i, label %if.else.i
if.then.i.i: ; preds = %entry
call void @llvm.memcpy.p5i8.p5i8.i64(i8 addrspace(5)* align 16 %cast, i8 addrspace(5)* align 4 undef, i64 128, i1 false)
br label %if.then.i62.i
if.else.i: ; preds = %entry
br label %if.then.i62.i
if.then.i62.i: ; preds = %if.else.i, %if.then.i.i
call void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* align 4 undef, i8 addrspace(5)* align 16 %cast, i64 128, i1 false)
ret void
}
declare void @llvm.memcpy.p5i8.p5i8.i64(i8 addrspace(5)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i1 immarg)
declare void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i1 immarg)