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[AMDGPU] Do not combine dpp with physreg def

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We will remove dpp mov along with the physreg def otherwise.

Differential Revision: https://reviews.llvm.org/D69063

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@375030 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Stanislav Mekhanoshin
2019-10-16 18:48:54 +00:00
parent ca30c1a99c
commit 139b3c56f6
2 changed files with 16 additions and 0 deletions
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lib/Target/AMDGPU/GCNDPPCombine.cpp
+4
View File
@@ -353,6 +353,10 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
auto *DstOpnd = TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst);
assert(DstOpnd && DstOpnd->isReg());
auto DPPMovReg = DstOpnd->getReg();
if (DPPMovReg.isPhysical()) {
LLVM_DEBUG(dbgs() << " failed: dpp move writes physreg\n");
return false;
}
if (execMayBeModifiedBeforeAnyUse(*MRI, DPPMovReg, MovMI)) {
LLVM_DEBUG(dbgs() << " failed: EXEC mask should remain the same"
" for all uses\n");
test/CodeGen/AMDGPU/dpp_combine.mir
+12
View File
@@ -563,6 +563,18 @@ body: |
%3:vgpr_32 = V_CEIL_F32_e32 %2, implicit $exec
...
# Do not combine a dpp mov which writes a physreg.
# GCN-LABEL: name: phys_dpp_mov_dst
# GCN: $vgpr0 = V_MOV_B32_dpp undef %0:vgpr_32, undef %1:vgpr_32, 1, 15, 15, 1, implicit $exec
# GCN: %2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
name: phys_dpp_mov_dst
tracksRegLiveness: true
body: |
bb.0:
$vgpr0 = V_MOV_B32_dpp undef %1:vgpr_32, undef %0:vgpr_32, 1, 15, 15, 1, implicit $exec
%2:vgpr_32 = V_CEIL_F32_e32 $vgpr0, implicit $exec
...
# GCN-LABEL: name: dpp_reg_sequence_both_combined
# GCN: %0:vreg_64 = COPY $vgpr0_vgpr1
# GCN: %1:vreg_64 = COPY $vgpr2_vgpr3