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[AMDGPU] Regenerate tests.
To help show the diffs from an upcoming SimplifyDemandedBits patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367175 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Pilgrim
File diff suppressed because it is too large
Load Diff
@@ -1,15 +1,50 @@
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,SI
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; RUN: llc < %s -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s -check-prefixes=GCN,VI
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; XXX - Why the packing?
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; GCN-LABEL: {{^}}scalar_to_vector_v2i32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]],
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; GCN: v_lshrrev_b32_e32 [[SHR:v[0-9]+]], 16, [[VAL]]
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; GCN: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 16, [[SHR]]
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; GCN: v_or_b32_e32 v[[OR:[0-9]+]], [[SHR]], [[SHL]]
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; GCN: v_mov_b32_e32 v[[COPY:[0-9]+]], v[[OR]]
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; GCN: buffer_store_dwordx2 v{{\[}}[[OR]]:[[COPY]]{{\]}}
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define amdgpu_kernel void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
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; SI-LABEL: scalar_to_vector_v2i32:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s10, s6
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s8, s2
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; SI-NEXT: s_mov_b32 s9, s3
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; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: v_mov_b32_e32 v1, v0
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v2i32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_mov_b32 s4, s6
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; VI-NEXT: s_mov_b32 s5, s7
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; VI-NEXT: s_mov_b32 s6, s2
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; VI-NEXT: s_mov_b32 s7, s3
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; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: v_mov_b32_e32 v1, v0
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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%tmp1 = load i32, i32 addrspace(1)* %in, align 4
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%bc = bitcast i32 %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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@@ -17,11 +52,48 @@ define amdgpu_kernel void @scalar_to_vector_v2i32(<4 x i16> addrspace(1)* %out,
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ret void
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}
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; GCN-LABEL: {{^}}scalar_to_vector_v2f32:
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; GCN: buffer_load_dword [[VAL:v[0-9]+]],
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; GCN: v_lshrrev_b32_e32 [[RESULT:v[0-9]+]], 16, [[VAL]]
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; GCN: buffer_store_dwordx2
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define amdgpu_kernel void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind {
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; SI-LABEL: scalar_to_vector_v2f32:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: s_mov_b32 s10, s6
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; SI-NEXT: s_mov_b32 s11, s7
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_mov_b32 s8, s2
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; SI-NEXT: s_mov_b32 s9, s3
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; SI-NEXT: buffer_load_dword v0, off, s[8:11], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
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; SI-NEXT: v_or_b32_e32 v0, v0, v1
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; SI-NEXT: s_mov_b32 s4, s0
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; SI-NEXT: s_mov_b32 s5, s1
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; SI-NEXT: v_mov_b32_e32 v1, v0
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v2f32:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_mov_b32 s4, s6
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; VI-NEXT: s_mov_b32 s5, s7
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; VI-NEXT: s_mov_b32 s6, s2
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; VI-NEXT: s_mov_b32 s7, s3
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; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v0
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; VI-NEXT: v_or_b32_e32 v0, v0, v1
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; VI-NEXT: v_mov_b32_e32 v1, v0
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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%tmp1 = load float, float addrspace(1)* %in, align 4
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%bc = bitcast float %tmp1 to <2 x i16>
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%tmp2 = shufflevector <2 x i16> %bc, <2 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
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@@ -29,14 +101,40 @@ define amdgpu_kernel void @scalar_to_vector_v2f32(<4 x i16> addrspace(1)* %out,
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ret void
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}
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; GCN-LABEL: {{^}}scalar_to_vector_v4i16:
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; VI: v_lshlrev_b16_e32
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; VI: v_lshlrev_b16_e32
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; VI: v_or_b32_e32
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; VI: v_lshlrev_b32
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; VI: v_or_b32_sdwa
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; VI: v_or_b32_sdwa
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define amdgpu_kernel void @scalar_to_vector_v4i16() {
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; SI-LABEL: scalar_to_vector_v4i16:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
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; SI-NEXT: v_or_b32_e32 v0, v1, v0
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; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
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; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v1
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; SI-NEXT: v_or_b32_e32 v1, v1, v2
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; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
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; SI-NEXT: v_or_b32_e32 v1, v1, v2
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; SI-NEXT: v_or_b32_e32 v0, v0, v2
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v4i16:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v0
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; VI-NEXT: v_or_b32_e32 v0, v1, v0
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; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v0
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; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v1
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; VI-NEXT: v_or_b32_e32 v1, v1, v2
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; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
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; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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bb:
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%tmp = load <2 x i8>, <2 x i8> addrspace(1)* undef, align 1
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%tmp1 = shufflevector <2 x i8> %tmp, <2 x i8> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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@@ -45,14 +143,40 @@ bb:
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ret void
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}
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; GCN-LABEL: {{^}}scalar_to_vector_v4f16:
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; VI: v_lshlrev_b16_e32
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; VI: v_lshlrev_b16_e32
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; VI: v_or_b32_e32
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; VI: v_lshlrev_b32
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; VI: v_or_b32_sdwa
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; VI: v_or_b32_sdwa
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define amdgpu_kernel void @scalar_to_vector_v4f16() {
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; SI-LABEL: scalar_to_vector_v4f16:
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; SI: ; %bb.0: ; %bb
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; SI-NEXT: s_mov_b32 s3, 0xf000
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; SI-NEXT: s_mov_b32 s2, -1
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; SI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; SI-NEXT: s_waitcnt vmcnt(0)
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; SI-NEXT: v_lshlrev_b32_e32 v1, 8, v0
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; SI-NEXT: v_or_b32_e32 v0, v1, v0
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; SI-NEXT: v_lshrrev_b32_e32 v1, 8, v0
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; SI-NEXT: v_lshlrev_b32_e32 v2, 8, v1
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; SI-NEXT: v_or_b32_e32 v1, v1, v2
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; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
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; SI-NEXT: v_or_b32_e32 v1, v1, v2
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; SI-NEXT: v_or_b32_e32 v0, v0, v2
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; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_v4f16:
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; VI: ; %bb.0: ; %bb
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: buffer_load_ubyte v0, off, s[0:3], 0
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v0
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; VI-NEXT: v_or_b32_e32 v0, v1, v0
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; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v0
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; VI-NEXT: v_lshlrev_b16_e32 v2, 8, v1
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; VI-NEXT: v_or_b32_e32 v1, v1, v2
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; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v1
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; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: v_or_b32_sdwa v0, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
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; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; VI-NEXT: s_endpgm
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bb:
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%load = load half, half addrspace(1)* undef, align 1
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%tmp = bitcast half %load to <2 x i8>
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@@ -101,6 +225,29 @@ bb:
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; }
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define amdgpu_kernel void @scalar_to_vector_test6(<2 x half> addrspace(1)* %out, i8 zeroext %val) nounwind {
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; SI-LABEL: scalar_to_vector_test6:
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; SI: ; %bb.0:
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; SI-NEXT: s_load_dword s2, s[0:1], 0xb
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; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
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; SI-NEXT: s_mov_b32 s7, 0xf000
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; SI-NEXT: s_waitcnt lgkmcnt(0)
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; SI-NEXT: s_and_b32 s0, s2, 0xff
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; SI-NEXT: s_mov_b32 s6, -1
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; SI-NEXT: v_mov_b32_e32 v0, s0
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; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; SI-NEXT: s_endpgm
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;
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; VI-LABEL: scalar_to_vector_test6:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
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; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_and_b32 s0, s0, 0xff
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; VI-NEXT: s_endpgm
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%newvec0 = insertelement <4 x i8> undef, i8 %val, i32 0
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%bc = bitcast <4 x i8> %newvec0 to <2 x half>
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store <2 x half> %bc, <2 x half> addrspace(1)* %out
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@@ -1,33 +1,48 @@
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; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=GCN,SI
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; RUN: llc < %s -march=amdgcn -mcpu=fiji -verify-machineinstrs | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI
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; Make sure high constant 0 isn't pointlessly materialized
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; GCN-LABEL: {{^}}trunc_bitcast_i64_lshr_32_i16:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64
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define i16 @trunc_bitcast_i64_lshr_32_i16(i64 %bar) {
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; GCN-LABEL: trunc_bitcast_i64_lshr_32_i16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%srl = lshr i64 %bar, 32
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%trunc = trunc i64 %srl to i16
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ret i16 %trunc
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}
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; GCN-LABEL: {{^}}trunc_bitcast_i64_lshr_32_i32:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64
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define i32 @trunc_bitcast_i64_lshr_32_i32(i64 %bar) {
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; GCN-LABEL: trunc_bitcast_i64_lshr_32_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, v1
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; GCN-NEXT: s_setpc_b64 s[30:31]
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%srl = lshr i64 %bar, 32
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%trunc = trunc i64 %srl to i32
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ret i32 %trunc
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}
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; GCN-LABEL: {{^}}trunc_bitcast_v2i32_to_i16:
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; GCN: _load_dword
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; GCN-NOT: _load_dword
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; GCN-NOT: v_mov_b32
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; VI: v_add_u16_e32 v0, 4, v0
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define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
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; SI-LABEL: trunc_bitcast_v2i32_to_i16:
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; SI: ; %bb.0:
|
||||
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
|
||||
; SI-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; VI-LABEL: trunc_bitcast_v2i32_to_i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: flat_load_dword v0, v[0:1]
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_add_u16_e32 v0, 4, v0
|
||||
; VI-NEXT: s_setpc_b64 s[30:31]
|
||||
%load0 = load i32, i32 addrspace(1)* undef
|
||||
%load1 = load i32, i32 addrspace(1)* null
|
||||
%insert.0 = insertelement <2 x i32> undef, i32 %load0, i32 0
|
||||
@@ -39,12 +54,24 @@ define i16 @trunc_bitcast_v2i32_to_i16(<2 x i32> %bar) {
|
||||
}
|
||||
|
||||
; Make sure there's no crash if the source vector type is FP
|
||||
; GCN-LABEL: {{^}}trunc_bitcast_v2f32_to_i16:
|
||||
; GCN: _load_dword
|
||||
; GCN-NOT: _load_dword
|
||||
; GCN-NOT: v_mov_b32
|
||||
; VI: v_add_u16_e32 v0, 4, v0
|
||||
define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
|
||||
; SI-LABEL: trunc_bitcast_v2f32_to_i16:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; SI-NEXT: s_mov_b32 s7, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s6, -1
|
||||
; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0
|
||||
; SI-NEXT: s_waitcnt vmcnt(0)
|
||||
; SI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
|
||||
; SI-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; VI-LABEL: trunc_bitcast_v2f32_to_i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: flat_load_dword v0, v[0:1]
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_add_u16_e32 v0, 4, v0
|
||||
; VI-NEXT: s_setpc_b64 s[30:31]
|
||||
%load0 = load float, float addrspace(1)* undef
|
||||
%load1 = load float, float addrspace(1)* null
|
||||
%insert.0 = insertelement <2 x float> undef, float %load0, i32 0
|
||||
@@ -55,14 +82,42 @@ define i16 @trunc_bitcast_v2f32_to_i16(<2 x float> %bar) {
|
||||
ret i16 %add
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}truncate_high_elt_extract_vector:
|
||||
; GCN: s_load_dword s
|
||||
; GCN: s_load_dword s
|
||||
; GCN: s_sext_i32_i16
|
||||
; GCN: s_sext_i32_i16
|
||||
; GCN: v_mul_i32_i24
|
||||
; GCN: v_lshrrev_b32_e32
|
||||
define amdgpu_kernel void @truncate_high_elt_extract_vector(<2 x i16> addrspace(1)* nocapture readonly %arg, <2 x i16> addrspace(1)* nocapture readonly %arg1, <2 x i16> addrspace(1)* nocapture %arg2) local_unnamed_addr {
|
||||
; SI-LABEL: truncate_high_elt_extract_vector:
|
||||
; SI: ; %bb.0: ; %bb
|
||||
; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
|
||||
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
|
||||
; SI-NEXT: s_mov_b32 s3, 0xf000
|
||||
; SI-NEXT: s_mov_b32 s2, -1
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_load_dword s4, s[4:5], 0x0
|
||||
; SI-NEXT: s_load_dword s5, s[6:7], 0x0
|
||||
; SI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; SI-NEXT: s_sext_i32_i16 s4, s4
|
||||
; SI-NEXT: s_sext_i32_i16 s5, s5
|
||||
; SI-NEXT: v_mov_b32_e32 v0, s4
|
||||
; SI-NEXT: v_mul_i32_i24_e32 v0, s5, v0
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
|
||||
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
||||
; SI-NEXT: s_endpgm
|
||||
;
|
||||
; VI-LABEL: truncate_high_elt_extract_vector:
|
||||
; VI: ; %bb.0: ; %bb
|
||||
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
||||
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_load_dword s2, s[4:5], 0x0
|
||||
; VI-NEXT: s_load_dword s3, s[6:7], 0x0
|
||||
; VI-NEXT: v_mov_b32_e32 v0, s0
|
||||
; VI-NEXT: v_mov_b32_e32 v1, s1
|
||||
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
||||
; VI-NEXT: s_sext_i32_i16 s0, s2
|
||||
; VI-NEXT: s_sext_i32_i16 s1, s3
|
||||
; VI-NEXT: v_mov_b32_e32 v2, s0
|
||||
; VI-NEXT: v_mul_i32_i24_e32 v2, s1, v2
|
||||
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
|
||||
; VI-NEXT: flat_store_dword v[0:1], v2
|
||||
; VI-NEXT: s_endpgm
|
||||
bb:
|
||||
%tmp = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %arg, i64 undef
|
||||
%tmp3 = load <2 x i16>, <2 x i16> addrspace(1)* %tmp, align 4
|
||||
@@ -82,17 +137,22 @@ bb:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}trunc_v2i64_arg_to_v2i16:
|
||||
; GCN: v_lshlrev_b32_e32 v1, 16, v2
|
||||
|
||||
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
||||
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
|
||||
; GCN-NEXT: s_setpc_b64
|
||||
define <2 x i16> @trunc_v2i64_arg_to_v2i16(<2 x i64> %arg0) #0 {
|
||||
; SI-LABEL: trunc_v2i64_arg_to_v2i16:
|
||||
; SI: ; %bb.0:
|
||||
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
||||
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
||||
; SI-NEXT: v_or_b32_e32 v0, v0, v1
|
||||
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
||||
; SI-NEXT: s_setpc_b64 s[30:31]
|
||||
;
|
||||
; VI-LABEL: trunc_v2i64_arg_to_v2i16:
|
||||
; VI: ; %bb.0:
|
||||
; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
||||
; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2
|
||||
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
||||
; VI-NEXT: s_setpc_b64 s[30:31]
|
||||
%trunc = trunc <2 x i64> %arg0 to <2 x i16>
|
||||
ret <2 x i16> %trunc
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user