mirror of
https://github.com/RPCS3/llvm.git
synced 2026-07-19 15:13:49 -04:00
[WebAssembly] SIMD Load and extend operations
Summary: As specified at https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend. These instructions are behind the unimplemented-simd128 target feature for now because they have not been implemented in V8 yet. Reviewers: aheejin Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68058 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373040 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Thomas Lively
@@ -332,6 +332,18 @@ inline unsigned GetDefaultP2AlignAny(unsigned Opc) {
|
||||
case WebAssembly::ATOMIC_WAIT_I64_S:
|
||||
case WebAssembly::LOAD_SPLAT_v64x2:
|
||||
case WebAssembly::LOAD_SPLAT_v64x2_S:
|
||||
case WebAssembly::LOAD_EXTEND_S_v8i16:
|
||||
case WebAssembly::LOAD_EXTEND_S_v8i16_S:
|
||||
case WebAssembly::LOAD_EXTEND_U_v8i16:
|
||||
case WebAssembly::LOAD_EXTEND_U_v8i16_S:
|
||||
case WebAssembly::LOAD_EXTEND_S_v4i32:
|
||||
case WebAssembly::LOAD_EXTEND_S_v4i32_S:
|
||||
case WebAssembly::LOAD_EXTEND_U_v4i32:
|
||||
case WebAssembly::LOAD_EXTEND_U_v4i32_S:
|
||||
case WebAssembly::LOAD_EXTEND_S_v2i64:
|
||||
case WebAssembly::LOAD_EXTEND_S_v2i64_S:
|
||||
case WebAssembly::LOAD_EXTEND_U_v2i64:
|
||||
case WebAssembly::LOAD_EXTEND_U_v2i64_S:
|
||||
return 3;
|
||||
case WebAssembly::LOAD_V128:
|
||||
case WebAssembly::LOAD_V128_S:
|
||||
|
||||
@@ -228,7 +228,7 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
|
||||
// - Floating-point extending loads.
|
||||
// - Floating-point truncating stores.
|
||||
// - i1 extending loads.
|
||||
// - extending/truncating SIMD loads/stores
|
||||
// - truncating SIMD stores and most extending loads
|
||||
setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
|
||||
setTruncStoreAction(MVT::f64, MVT::f32, Expand);
|
||||
for (auto T : MVT::integer_valuetypes())
|
||||
@@ -245,6 +245,14 @@ WebAssemblyTargetLowering::WebAssemblyTargetLowering(
|
||||
}
|
||||
}
|
||||
}
|
||||
// But some vector extending loads are legal
|
||||
if (Subtarget->hasUnimplementedSIMD128()) {
|
||||
for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
|
||||
setLoadExtAction(Ext, MVT::v8i16, MVT::v8i8, Legal);
|
||||
setLoadExtAction(Ext, MVT::v4i32, MVT::v4i16, Legal);
|
||||
setLoadExtAction(Ext, MVT::v2i64, MVT::v2i32, Legal);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Don't do anything clever with build_pairs
|
||||
@@ -540,6 +548,16 @@ bool WebAssemblyTargetLowering::isIntDivCheap(EVT VT,
|
||||
return true;
|
||||
}
|
||||
|
||||
bool WebAssemblyTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
|
||||
if (!Subtarget->hasUnimplementedSIMD128())
|
||||
return false;
|
||||
MVT ExtT = ExtVal.getSimpleValueType();
|
||||
MVT MemT = cast<LoadSDNode>(ExtVal->getOperand(0))->getSimpleValueType(0);
|
||||
return (ExtT == MVT::v8i16 && MemT == MVT::v8i8) ||
|
||||
(ExtT == MVT::v4i32 && MemT == MVT::v4i16) ||
|
||||
(ExtT == MVT::v2i64 && MemT == MVT::v2i32);
|
||||
}
|
||||
|
||||
EVT WebAssemblyTargetLowering::getSetCCResultType(const DataLayout &DL,
|
||||
LLVMContext &C,
|
||||
EVT VT) const {
|
||||
|
||||
@@ -63,7 +63,7 @@ private:
|
||||
MachineMemOperand::Flags Flags,
|
||||
bool *Fast) const override;
|
||||
bool isIntDivCheap(EVT VT, AttributeList Attr) const override;
|
||||
|
||||
bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
|
||||
EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
|
||||
EVT VT) const override;
|
||||
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
|
||||
|
||||
@@ -104,6 +104,45 @@ def : LoadPatGlobalAddrOffOnly<!cast<ValueType>(args[0]),
|
||||
!cast<NI>("LOAD_SPLAT_"#args[1])>;
|
||||
}
|
||||
|
||||
// Load and extend
|
||||
multiclass SIMDLoadExtend<ValueType vec_t, string name, bits<32> simdop> {
|
||||
let mayLoad = 1, UseNamedOperandTable = 1,
|
||||
Predicates = [HasUnimplementedSIMD128] in {
|
||||
defm LOAD_EXTEND_S_#vec_t :
|
||||
SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
|
||||
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
||||
name#"_s\t$dst, ${off}(${addr})$p2align",
|
||||
name#"_s\t$off$p2align", simdop>;
|
||||
defm LOAD_EXTEND_U_#vec_t :
|
||||
SIMD_I<(outs V128:$dst), (ins P2Align:$p2align, offset32_op:$off, I32:$addr),
|
||||
(outs), (ins P2Align:$p2align, offset32_op:$off), [],
|
||||
name#"_u\t$dst, ${off}(${addr})$p2align",
|
||||
name#"_u\t$off$p2align", !add(simdop, 1)>;
|
||||
}
|
||||
}
|
||||
|
||||
defm "" : SIMDLoadExtend<v8i16, "i16x8.load8x8", 210>;
|
||||
defm "" : SIMDLoadExtend<v4i32, "i32x4.load16x4", 212>;
|
||||
defm "" : SIMDLoadExtend<v2i64, "i64x2.load32x2", 214>;
|
||||
|
||||
let Predicates = [HasUnimplementedSIMD128] in
|
||||
foreach types = [[v8i16, i8], [v4i32, i16], [v2i64, i32]] in
|
||||
foreach exts = [["sextloadv", "_S"],
|
||||
["zextloadv", "_U"],
|
||||
["extloadv", "_U"]] in {
|
||||
def : LoadPatNoOffset<types[0], !cast<PatFrag>(exts[0]#types[1]),
|
||||
!cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
|
||||
def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), regPlusImm,
|
||||
!cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
|
||||
def : LoadPatImmOff<types[0], !cast<PatFrag>(exts[0]#types[1]), or_is_add,
|
||||
!cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
|
||||
def : LoadPatOffsetOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
|
||||
!cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
|
||||
def : LoadPatGlobalAddrOffOnly<types[0], !cast<PatFrag>(exts[0]#types[1]),
|
||||
!cast<NI>("LOAD_EXTEND"#exts[1]#"_"#types[0])>;
|
||||
}
|
||||
|
||||
|
||||
// Store: v128.store
|
||||
let mayStore = 1, UseNamedOperandTable = 1 in
|
||||
defm STORE_V128 :
|
||||
|
||||
@@ -1,57 +0,0 @@
|
||||
; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+unimplemented-simd128 | FileCheck %s
|
||||
|
||||
; Check that store in memory with smaller lanes are loaded and stored
|
||||
; as expected. This is a regression test for part of bug 39275.
|
||||
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
|
||||
target triple = "wasm32-unknown-unknown"
|
||||
|
||||
; CHECK-LABEL: load_ext_2xi32:
|
||||
; CHECK-NEXT: .functype load_ext_2xi32 (i32) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
|
||||
; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
|
||||
; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
|
||||
; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i32> @load_ext_2xi32(<2 x i32>* %p) {
|
||||
%1 = load <2 x i32>, <2 x i32>* %p, align 4
|
||||
ret <2 x i32> %1
|
||||
}
|
||||
|
||||
; CHECK-LABEL: load_zext_2xi32:
|
||||
; CHECK-NEXT: .functype load_zext_2xi32 (i32) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64.load32_u $push[[L0:[0-9]+]]=, 0($0){{$}}
|
||||
; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
|
||||
; CHECK-NEXT: i64.load32_u $push[[L2:[0-9]+]]=, 4($0){{$}}
|
||||
; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i64> @load_zext_2xi32(<2 x i32>* %p) {
|
||||
%1 = load <2 x i32>, <2 x i32>* %p, align 4
|
||||
%2 = zext <2 x i32> %1 to <2 x i64>
|
||||
ret <2 x i64> %2
|
||||
}
|
||||
|
||||
; CHECK-LABEL: load_sext_2xi32:
|
||||
; CHECK-NEXT: .functype load_sext_2xi32 (i32) -> (v128){{$}}
|
||||
; CHECK-NEXT: i64.load32_s $push[[L0:[0-9]+]]=, 0($0){{$}}
|
||||
; CHECK-NEXT: i64x2.splat $push[[L1:[0-9]+]]=, $pop[[L0]]{{$}}
|
||||
; CHECK-NEXT: i64.load32_s $push[[L2:[0-9]+]]=, 4($0){{$}}
|
||||
; CHECK-NEXT: i64x2.replace_lane $push[[R:[0-9]+]]=, $pop[[L1]], 1, $pop[[L2]]{{$}}
|
||||
; CHECK-NEXT: return $pop[[R]]{{$}}
|
||||
define <2 x i64> @load_sext_2xi32(<2 x i32>* %p) {
|
||||
%1 = load <2 x i32>, <2 x i32>* %p, align 4
|
||||
%2 = sext <2 x i32> %1 to <2 x i64>
|
||||
ret <2 x i64> %2
|
||||
}
|
||||
|
||||
; CHECK-LABEL: store_trunc_2xi32:
|
||||
; CHECK-NEXT: .functype store_trunc_2xi32 (i32, v128) -> (){{$}}
|
||||
; CHECK-NEXT: i64x2.extract_lane $push[[L0:[0-9]+]]=, $1, 1
|
||||
; CHECK-NEXT: i64.store32 4($0), $pop[[L0]]
|
||||
; CHECK-NEXT: i64x2.extract_lane $push[[L1:[0-9]+]]=, $1, 0
|
||||
; CHECK-NEXT: i64.store32 0($0), $pop[[L1]]
|
||||
; CHECK-NEXT: return
|
||||
define void @store_trunc_2xi32(<2 x i32>* %p, <2 x i32> %x) {
|
||||
store <2 x i32> %x, <2 x i32>* %p, align 4
|
||||
ret void
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -511,4 +511,22 @@ main:
|
||||
# CHECK: i32x4.widen_high_i16x8_u # encoding: [0xfd,0xd1,0x01]
|
||||
i32x4.widen_high_i16x8_u
|
||||
|
||||
# CHECK: i16x8.load8x8_s 32 # encoding: [0xfd,0xd2,0x01,0x03,0x20]
|
||||
i16x8.load8x8_s 32
|
||||
|
||||
# CHECK: i16x8.load8x8_u 32 # encoding: [0xfd,0xd3,0x01,0x03,0x20]
|
||||
i16x8.load8x8_u 32
|
||||
|
||||
# CHECK: i32x4.load16x4_s 32 # encoding: [0xfd,0xd4,0x01,0x03,0x20]
|
||||
i32x4.load16x4_s 32
|
||||
|
||||
# CHECK: i32x4.load16x4_u 32 # encoding: [0xfd,0xd5,0x01,0x03,0x20]
|
||||
i32x4.load16x4_u 32
|
||||
|
||||
# CHECK: i64x2.load32x2_s 32 # encoding: [0xfd,0xd6,0x01,0x03,0x20]
|
||||
i64x2.load32x2_s 32
|
||||
|
||||
# CHECK: i64x2.load32x2_u 32 # encoding: [0xfd,0xd7,0x01,0x03,0x20]
|
||||
i64x2.load32x2_u 32
|
||||
|
||||
end_function
|
||||
|
||||
Reference in New Issue
Block a user