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ARM64: make sure FastISel emits SSA MachineInstrs

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We need to use a temporary register for a 2-step operation like REM.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208297 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover 2014-05-08 10:30:56 +00:00
parent 89329e902c
commit 291cd09645
2 changed files with 23 additions and 11 deletions
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7
lib/Target/ARM64/ARM64FastISel.cpp
View File

@ -1849,14 +1849,15 @@ bool ARM64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
if (!Src1Reg)
return false;
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), ResultReg)
unsigned QuotReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(DivOpc), QuotReg)
.addReg(Src0Reg)
.addReg(Src1Reg);
// The remainder is computed as numerator - (quotient * denominator) using the
// MSUB instruction.
unsigned ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MSubOpc), ResultReg)
.addReg(ResultReg)
.addReg(QuotReg)
.addReg(Src1Reg)
.addReg(Src0Reg);
UpdateValueMap(I, ResultReg);

27
test/CodeGen/ARM64/fast-isel-rem.ll
View File

@ -1,33 +1,44 @@
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
; REQUIRES: asserts
; CHECK-SSA-LABEL: Machine code for function t1
; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
; CHECK-SSA-NOT: [[QUOTREG]]<def> =
; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
; CHECK-SSA-LABEL: Machine code for function t2
define i32 @t1(i32 %a, i32 %b) {
; CHECK: @t1
; CHECK: sdiv w2, w0, w1
; CHECK: msub w2, w2, w1, w0
; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
; CHECK: msub w0, [[TMP]], w1, w0
%1 = srem i32 %a, %b
ret i32 %1
}
define i64 @t2(i64 %a, i64 %b) {
; CHECK: @t2
; CHECK: sdiv x2, x0, x1
; CHECK: msub x2, x2, x1, x0
; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
; CHECK: msub x0, [[TMP]], x1, x0
%1 = srem i64 %a, %b
ret i64 %1
}
define i32 @t3(i32 %a, i32 %b) {
; CHECK: @t3
; CHECK: udiv w2, w0, w1
; CHECK: msub w2, w2, w1, w0
; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
; CHECK: msub w0, [[TMP]], w1, w0
%1 = urem i32 %a, %b
ret i32 %1
}
define i64 @t4(i64 %a, i64 %b) {
; CHECK: @t4
; CHECK: udiv x2, x0, x1
; CHECK: msub x2, x2, x1, x0
; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
; CHECK: msub x0, [[TMP]], x1, x0
%1 = urem i64 %a, %b
ret i64 %1
}